drm/radeon/kms: add cayman CS check support
Added to existing evergreen CS checker. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Родитель
e348762955
Коммит
c175ca9a4c
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@ -53,7 +53,7 @@ $(obj)/rs600.o: $(obj)/rs600_reg_safe.h
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$(obj)/r600_cs.o: $(obj)/r600_reg_safe.h
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$(obj)/r600_cs.o: $(obj)/r600_reg_safe.h
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$(obj)/evergreen_cs.o: $(obj)/evergreen_reg_safe.h
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$(obj)/evergreen_cs.o: $(obj)/evergreen_reg_safe.h $(obj)/cayman_reg_safe.h
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radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \
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radeon-y := radeon_drv.o radeon_cp.o radeon_state.o radeon_mem.o \
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radeon_irq.o r300_cmdbuf.o r600_cp.o
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radeon_irq.o r300_cmdbuf.o r600_cp.o
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@ -29,6 +29,7 @@
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#include "radeon.h"
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#include "radeon.h"
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#include "evergreend.h"
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#include "evergreend.h"
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#include "evergreen_reg_safe.h"
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#include "evergreen_reg_safe.h"
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#include "cayman_reg_safe.h"
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static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
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static int evergreen_cs_packet_next_reloc(struct radeon_cs_parser *p,
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struct radeon_cs_reloc **cs_reloc);
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struct radeon_cs_reloc **cs_reloc);
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@ -425,18 +426,28 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3
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{
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{
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struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track;
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struct evergreen_cs_track *track = (struct evergreen_cs_track *)p->track;
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struct radeon_cs_reloc *reloc;
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struct radeon_cs_reloc *reloc;
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u32 last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
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u32 last_reg;
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u32 m, i, tmp, *ib;
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u32 m, i, tmp, *ib;
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int r;
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int r;
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if (p->rdev->family >= CHIP_CAYMAN)
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last_reg = ARRAY_SIZE(cayman_reg_safe_bm);
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else
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last_reg = ARRAY_SIZE(evergreen_reg_safe_bm);
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i = (reg >> 7);
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i = (reg >> 7);
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if (i > last_reg) {
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if (i > last_reg) {
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dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
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dev_warn(p->dev, "forbidden register 0x%08x at %d\n", reg, idx);
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return -EINVAL;
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return -EINVAL;
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}
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}
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m = 1 << ((reg >> 2) & 31);
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m = 1 << ((reg >> 2) & 31);
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if (p->rdev->family >= CHIP_CAYMAN) {
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if (!(cayman_reg_safe_bm[i] & m))
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return 0;
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} else {
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if (!(evergreen_reg_safe_bm[i] & m))
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if (!(evergreen_reg_safe_bm[i] & m))
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return 0;
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return 0;
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}
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ib = p->ib->ptr;
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ib = p->ib->ptr;
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switch (reg) {
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switch (reg) {
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/* force following reg to 0 in an attemp to disable out buffer
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/* force following reg to 0 in an attemp to disable out buffer
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@ -474,6 +485,20 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3
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case DB_DEPTH_CONTROL:
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case DB_DEPTH_CONTROL:
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track->db_depth_control = radeon_get_ib_value(p, idx);
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track->db_depth_control = radeon_get_ib_value(p, idx);
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break;
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break;
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case CAYMAN_DB_EQAA:
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if (p->rdev->family < CHIP_CAYMAN) {
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dev_warn(p->dev, "bad SET_CONTEXT_REG "
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"0x%04X\n", reg);
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return -EINVAL;
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}
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break;
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case CAYMAN_DB_DEPTH_INFO:
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if (p->rdev->family < CHIP_CAYMAN) {
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dev_warn(p->dev, "bad SET_CONTEXT_REG "
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"0x%04X\n", reg);
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return -EINVAL;
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}
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break;
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case DB_Z_INFO:
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case DB_Z_INFO:
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r = evergreen_cs_packet_next_reloc(p, &reloc);
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r = evergreen_cs_packet_next_reloc(p, &reloc);
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if (r) {
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if (r) {
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@ -559,9 +584,23 @@ static inline int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u3
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track->cb_shader_mask = radeon_get_ib_value(p, idx);
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track->cb_shader_mask = radeon_get_ib_value(p, idx);
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break;
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break;
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case PA_SC_AA_CONFIG:
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case PA_SC_AA_CONFIG:
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if (p->rdev->family >= CHIP_CAYMAN) {
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dev_warn(p->dev, "bad SET_CONTEXT_REG "
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"0x%04X\n", reg);
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return -EINVAL;
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}
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tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK;
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tmp = radeon_get_ib_value(p, idx) & MSAA_NUM_SAMPLES_MASK;
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track->nsamples = 1 << tmp;
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track->nsamples = 1 << tmp;
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break;
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break;
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case CAYMAN_PA_SC_AA_CONFIG:
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if (p->rdev->family < CHIP_CAYMAN) {
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dev_warn(p->dev, "bad SET_CONTEXT_REG "
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"0x%04X\n", reg);
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return -EINVAL;
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}
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tmp = radeon_get_ib_value(p, idx) & CAYMAN_MSAA_NUM_SAMPLES_MASK;
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track->nsamples = 1 << tmp;
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break;
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case CB_COLOR0_VIEW:
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case CB_COLOR0_VIEW:
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case CB_COLOR1_VIEW:
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case CB_COLOR1_VIEW:
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case CB_COLOR2_VIEW:
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case CB_COLOR2_VIEW:
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@ -987,6 +1026,16 @@ static int evergreen_packet3_check(struct radeon_cs_parser *p,
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return -EINVAL;
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return -EINVAL;
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}
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}
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break;
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break;
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case CAYMAN_PACKET3_DEALLOC_STATE:
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if (p->rdev->family < CHIP_CAYMAN) {
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DRM_ERROR("bad PACKET3_DEALLOC_STATE\n");
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return -EINVAL;
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}
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if (pkt->count) {
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DRM_ERROR("bad INDEX_TYPE/NUM_INSTANCES/CLEAR_STATE\n");
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return -EINVAL;
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}
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break;
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case PACKET3_INDEX_BASE:
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case PACKET3_INDEX_BASE:
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if (pkt->count != 1) {
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if (pkt->count != 1) {
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DRM_ERROR("bad INDEX_BASE\n");
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DRM_ERROR("bad INDEX_BASE\n");
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@ -1092,5 +1092,14 @@
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#define SQ_TEX_RESOURCE_WORD6_0 0x30018
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#define SQ_TEX_RESOURCE_WORD6_0 0x30018
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#define SQ_TEX_RESOURCE_WORD7_0 0x3001c
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#define SQ_TEX_RESOURCE_WORD7_0 0x3001c
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/* cayman 3D regs */
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#define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B0
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#define CAYMAN_DB_EQAA 0x28804
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#define CAYMAN_DB_DEPTH_INFO 0x2803C
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#define CAYMAN_PA_SC_AA_CONFIG 0x28BE0
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#define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0
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#define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7
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/* cayman packet3 addition */
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#define CAYMAN_PACKET3_DEALLOC_STATE 0x14
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#endif
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#endif
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