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WSL2-Linux-Kernel
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staging: wfx: prefix functions from hwio.h with wfx_ 

All the functions related to a driver should use the same prefix.

Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Link: https://lore.kernel.org/r/20220113085524.1110708-16-Jerome.Pouiller@silabs.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Jérôme Pouiller 2022-01-13 09:55:08 +01:00 коммит произвёл Greg Kroah-Hartman
Родитель 1c7804829b
Коммит c1d193c505
6 изменённых файлов: 133 добавлений и 124 удалений
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8
drivers/staging/wfx/bh.c
Просмотреть файл

@ -227,11 +227,11 @@ static void ack_sdio_data(struct wfx_dev *wdev)
{
u32 cfg_reg;
config_reg_read(wdev, &cfg_reg);
wfx_config_reg_read(wdev, &cfg_reg);
if (cfg_reg & 0xFF) {
dev_warn(wdev->dev, "chip reports errors: %02x\n",
cfg_reg & 0xFF);
config_reg_write_bits(wdev, 0xFF, 0x00);
wfx_config_reg_write_bits(wdev, 0xFF, 0x00);
}
}
@ -270,7 +270,7 @@ void wfx_bh_request_rx(struct wfx_dev *wdev)
{
u32 cur, prev;
control_reg_read(wdev, &cur);
wfx_control_reg_read(wdev, &cur);
prev = atomic_xchg(&wdev->hif.ctrl_reg, cur);
complete(&wdev->hif.ctrl_ready);
queue_work(system_highpri_wq, &wdev->hif.bh);
@ -304,7 +304,7 @@ void wfx_bh_poll_irq(struct wfx_dev *wdev)
WARN(!wdev->poll_irq, "unexpected IRQ polling can mask IRQ");
start = ktime_get();
for (;;) {
control_reg_read(wdev, &reg);
wfx_control_reg_read(wdev, &reg);
now = ktime_get();
if (reg & 0xFFF)
break;

78
drivers/staging/wfx/fwio.c
Просмотреть файл

@ -79,8 +79,8 @@ static const char * const fwio_errors[] = {
* NOTE: it may also be possible to use 'pages' from struct firmware and avoid
* bounce buffer
*/
static int sram_write_dma_safe(struct wfx_dev *wdev, u32 addr, const u8 *buf,
size_t len)
static int wfx_sram_write_dma_safe(struct wfx_dev *wdev, u32 addr,
const u8 *buf, size_t len)
{
int ret;
const u8 *tmp;
@ -92,7 +92,7 @@ static int sram_write_dma_safe(struct wfx_dev *wdev, u32 addr, const u8 *buf,
} else {
tmp = buf;
}
ret = sram_buf_write(wdev, addr, tmp, len);
ret = wfx_sram_buf_write(wdev, addr, tmp, len);
if (tmp != buf)
kfree(tmp);
return ret;
@ -156,7 +156,7 @@ static int wait_ncp_status(struct wfx_dev *wdev, u32 status)
start = ktime_get();
for (;;) {
ret = sram_reg_read(wdev, WFX_DCA_NCP_STATUS, &reg);
ret = wfx_sram_reg_read(wdev, WFX_DCA_NCP_STATUS, &reg);
if (ret < 0)
return -EIO;
now = ktime_get();
@ -192,7 +192,7 @@ static int upload_firmware(struct wfx_dev *wdev, const u8 *data, size_t len)
break;
if (ktime_after(now, ktime_add_ms(start, DCA_TIMEOUT)))
return -ETIMEDOUT;
ret = sram_reg_read(wdev, WFX_DCA_GET, &bytes_done);
ret = wfx_sram_reg_read(wdev, WFX_DCA_GET, &bytes_done);
if (ret < 0)
return ret;
}
@ -200,9 +200,9 @@ static int upload_firmware(struct wfx_dev *wdev, const u8 *data, size_t len)
dev_dbg(wdev->dev, "answer after %lldus\n",
ktime_us_delta(now, start));
ret = sram_write_dma_safe(wdev, WFX_DNLD_FIFO +
(offs % DNLD_FIFO_SIZE),
data + offs, DNLD_BLOCK_SIZE);
ret = wfx_sram_write_dma_safe(wdev,
WFX_DNLD_FIFO + (offs % DNLD_FIFO_SIZE),
data + offs, DNLD_BLOCK_SIZE);
if (ret < 0)
return ret;
@ -210,7 +210,7 @@ static int upload_firmware(struct wfx_dev *wdev, const u8 *data, size_t len)
* during first loop
*/
offs += DNLD_BLOCK_SIZE;
ret = sram_reg_write(wdev, WFX_DCA_PUT, offs);
ret = wfx_sram_reg_write(wdev, WFX_DCA_PUT, offs);
if (ret < 0)
return ret;
}
@ -221,10 +221,10 @@ static void print_boot_status(struct wfx_dev *wdev)
{
u32 reg;
sram_reg_read(wdev, WFX_STATUS_INFO, &reg);
wfx_sram_reg_read(wdev, WFX_STATUS_INFO, &reg);
if (reg == 0x12345678)
return;
sram_reg_read(wdev, WFX_ERR_INFO, &reg);
wfx_sram_reg_read(wdev, WFX_ERR_INFO, &reg);
if (reg < ARRAY_SIZE(fwio_errors) && fwio_errors[reg])
dev_info(wdev->dev, "secure boot: %s\n", fwio_errors[reg]);
else
@ -245,36 +245,36 @@ static int load_firmware_secure(struct wfx_dev *wdev)
if (!buf)
return -ENOMEM;
sram_reg_write(wdev, WFX_DCA_HOST_STATUS, HOST_READY);
wfx_sram_reg_write(wdev, WFX_DCA_HOST_STATUS, HOST_READY);
ret = wait_ncp_status(wdev, NCP_INFO_READY);
if (ret)
goto error;
sram_buf_read(wdev, WFX_BOOTLOADER_LABEL, buf, BOOTLOADER_LABEL_SIZE);
wfx_sram_buf_read(wdev, WFX_BOOTLOADER_LABEL, buf, BOOTLOADER_LABEL_SIZE);
buf[BOOTLOADER_LABEL_SIZE] = 0;
dev_dbg(wdev->dev, "bootloader: \"%s\"\n", buf);
sram_buf_read(wdev, WFX_PTE_INFO, buf, PTE_INFO_SIZE);
wfx_sram_buf_read(wdev, WFX_PTE_INFO, buf, PTE_INFO_SIZE);
ret = get_firmware(wdev, buf[PTE_INFO_KEYSET_IDX], &fw, &fw_offset);
if (ret)
goto error;
header_size = fw_offset + FW_SIGNATURE_SIZE + FW_HASH_SIZE;
sram_reg_write(wdev, WFX_DCA_HOST_STATUS, HOST_INFO_READ);
wfx_sram_reg_write(wdev, WFX_DCA_HOST_STATUS, HOST_INFO_READ);
ret = wait_ncp_status(wdev, NCP_READY);
if (ret)
goto error;
sram_reg_write(wdev, WFX_DNLD_FIFO, 0xFFFFFFFF); /* Fifo init */
sram_write_dma_safe(wdev, WFX_DCA_FW_VERSION, "\x01\x00\x00\x00",
FW_VERSION_SIZE);
sram_write_dma_safe(wdev, WFX_DCA_FW_SIGNATURE, fw->data + fw_offset,
FW_SIGNATURE_SIZE);
sram_write_dma_safe(wdev, WFX_DCA_FW_HASH,
fw->data + fw_offset + FW_SIGNATURE_SIZE,
FW_HASH_SIZE);
sram_reg_write(wdev, WFX_DCA_IMAGE_SIZE, fw->size - header_size);
sram_reg_write(wdev, WFX_DCA_HOST_STATUS, HOST_UPLOAD_PENDING);
wfx_sram_reg_write(wdev, WFX_DNLD_FIFO, 0xFFFFFFFF); /* Fifo init */
wfx_sram_write_dma_safe(wdev, WFX_DCA_FW_VERSION, "\x01\x00\x00\x00",
FW_VERSION_SIZE);
wfx_sram_write_dma_safe(wdev, WFX_DCA_FW_SIGNATURE, fw->data + fw_offset,
FW_SIGNATURE_SIZE);
wfx_sram_write_dma_safe(wdev, WFX_DCA_FW_HASH,
fw->data + fw_offset + FW_SIGNATURE_SIZE,
FW_HASH_SIZE);
wfx_sram_reg_write(wdev, WFX_DCA_IMAGE_SIZE, fw->size - header_size);
wfx_sram_reg_write(wdev, WFX_DCA_HOST_STATUS, HOST_UPLOAD_PENDING);
ret = wait_ncp_status(wdev, NCP_DOWNLOAD_PENDING);
if (ret)
goto error;
@ -287,14 +287,14 @@ static int load_firmware_secure(struct wfx_dev *wdev)
dev_dbg(wdev->dev, "firmware load after %lldus\n",
ktime_us_delta(ktime_get(), start));
sram_reg_write(wdev, WFX_DCA_HOST_STATUS, HOST_UPLOAD_COMPLETE);
wfx_sram_reg_write(wdev, WFX_DCA_HOST_STATUS, HOST_UPLOAD_COMPLETE);
ret = wait_ncp_status(wdev, NCP_AUTH_OK);
/* Legacy ROM support */
if (ret < 0)
ret = wait_ncp_status(wdev, NCP_PUB_KEY_RDY);
if (ret < 0)
goto error;
sram_reg_write(wdev, WFX_DCA_HOST_STATUS, HOST_OK_TO_JUMP);
wfx_sram_reg_write(wdev, WFX_DCA_HOST_STATUS, HOST_OK_TO_JUMP);
error:
kfree(buf);
@ -320,8 +320,8 @@ static int init_gpr(struct wfx_dev *wdev)
};
for (i = 0; i < ARRAY_SIZE(gpr_init); i++) {
ret = igpr_reg_write(wdev, gpr_init[i].index,
gpr_init[i].value);
ret = wfx_igpr_reg_write(wdev, gpr_init[i].index,
gpr_init[i].value);
if (ret < 0)
return ret;
dev_dbg(wdev->dev, " index %02x: %08x\n",
@ -341,13 +341,13 @@ int wfx_init_device(struct wfx_dev *wdev)
reg = CFG_DIRECT_ACCESS_MODE | CFG_CPU_RESET | CFG_BYTE_ORDER_ABCD;
if (wdev->pdata.use_rising_clk)
reg |= CFG_CLK_RISE_EDGE;
ret = config_reg_write(wdev, reg);
ret = wfx_config_reg_write(wdev, reg);
if (ret < 0) {
dev_err(wdev->dev, "bus returned an error during first write access. Host configuration error?\n");
return -EIO;
}
ret = config_reg_read(wdev, &reg);
ret = wfx_config_reg_read(wdev, &reg);
if (ret < 0) {
dev_err(wdev->dev, "bus returned an error during first read access. Bus configuration error?\n");
return -EIO;
@ -374,12 +374,12 @@ int wfx_init_device(struct wfx_dev *wdev)
if (ret < 0)
return ret;
ret = control_reg_write(wdev, CTRL_WLAN_WAKEUP);
ret = wfx_control_reg_write(wdev, CTRL_WLAN_WAKEUP);
if (ret < 0)
return -EIO;
start = ktime_get();
for (;;) {
ret = control_reg_read(wdev, &reg);
ret = wfx_control_reg_read(wdev, &reg);
now = ktime_get();
if (reg & CTRL_WLAN_READY)
break;
@ -391,15 +391,15 @@ int wfx_init_device(struct wfx_dev *wdev)
dev_dbg(wdev->dev, "chip wake up after %lldus\n",
ktime_us_delta(now, start));
ret = config_reg_write_bits(wdev, CFG_CPU_RESET, 0);
ret = wfx_config_reg_write_bits(wdev, CFG_CPU_RESET, 0);
if (ret < 0)
return ret;
ret = load_firmware_secure(wdev);
if (ret < 0)
return ret;
return config_reg_write_bits(wdev,
CFG_DIRECT_ACCESS_MODE |
CFG_IRQ_ENABLE_DATA |
CFG_IRQ_ENABLE_WRDY,
CFG_IRQ_ENABLE_DATA);
return wfx_config_reg_write_bits(wdev,
CFG_DIRECT_ACCESS_MODE |
CFG_IRQ_ENABLE_DATA |
CFG_IRQ_ENABLE_WRDY,
CFG_IRQ_ENABLE_DATA);
}

2
drivers/staging/wfx/hif_tx.c
Просмотреть файл

@ -135,7 +135,7 @@ int wfx_hif_shutdown(struct wfx_dev *wdev)
if (wdev->pdata.gpio_wakeup)
gpiod_set_value(wdev->pdata.gpio_wakeup, 0);
else
control_reg_write(wdev, 0);
wfx_control_reg_write(wdev, 0);
kfree(hif);
return ret;
}

135
drivers/staging/wfx/hwio.c
Просмотреть файл

@ -17,7 +17,7 @@
#define WFX_HIF_BUFFER_SIZE 0x2000
static int read32(struct wfx_dev *wdev, int reg, u32 *val)
static int wfx_read32(struct wfx_dev *wdev, int reg, u32 *val)
{
int ret;
__le32 *tmp = kmalloc(sizeof(u32), GFP_KERNEL);
@ -36,7 +36,7 @@ static int read32(struct wfx_dev *wdev, int reg, u32 *val)
return ret;
}
static int write32(struct wfx_dev *wdev, int reg, u32 val)
static int wfx_write32(struct wfx_dev *wdev, int reg, u32 val)
{
int ret;
__le32 *tmp = kmalloc(sizeof(u32), GFP_KERNEL);
@ -53,29 +53,30 @@ static int write32(struct wfx_dev *wdev, int reg, u32 val)
return ret;
}
static int read32_locked(struct wfx_dev *wdev, int reg, u32 *val)
static int wfx_read32_locked(struct wfx_dev *wdev, int reg, u32 *val)
{
int ret;
wdev->hwbus_ops->lock(wdev->hwbus_priv);
ret = read32(wdev, reg, val);
ret = wfx_read32(wdev, reg, val);
_trace_io_read32(reg, *val);
wdev->hwbus_ops->unlock(wdev->hwbus_priv);
return ret;
}
static int write32_locked(struct wfx_dev *wdev, int reg, u32 val)
static int wfx_write32_locked(struct wfx_dev *wdev, int reg, u32 val)
{
int ret;
wdev->hwbus_ops->lock(wdev->hwbus_priv);
ret = write32(wdev, reg, val);
ret = wfx_write32(wdev, reg, val);
_trace_io_write32(reg, val);
wdev->hwbus_ops->unlock(wdev->hwbus_priv);
return ret;
}
static int write32_bits_locked(struct wfx_dev *wdev, int reg, u32 mask, u32 val)
static int wfx_write32_bits_locked(struct wfx_dev *wdev,
int reg, u32 mask, u32 val)
{
int ret;
u32 val_r, val_w;
@ -83,13 +84,13 @@ static int write32_bits_locked(struct wfx_dev *wdev, int reg, u32 mask, u32 val)
WARN_ON(~mask & val);
val &= mask;
wdev->hwbus_ops->lock(wdev->hwbus_priv);
ret = read32(wdev, reg, &val_r);
ret = wfx_read32(wdev, reg, &val_r);
_trace_io_read32(reg, val_r);
if (ret < 0)
goto err;
val_w = (val_r & ~mask) | val;
if (val_w != val_r) {
ret = write32(wdev, reg, val_w);
ret = wfx_write32(wdev, reg, val_w);
_trace_io_write32(reg, val_w);
}
err:
@ -97,8 +98,8 @@ err:
return ret;
}
static int indirect_read(struct wfx_dev *wdev, int reg, u32 addr,
void *buf, size_t len)
static int wfx_indirect_read(struct wfx_dev *wdev, int reg, u32 addr,
void *buf, size_t len)
{
int ret;
int i;
@ -115,20 +116,20 @@ static int indirect_read(struct wfx_dev *wdev, int reg, u32 addr,
else
return -ENODEV;
ret = write32(wdev, WFX_REG_BASE_ADDR, addr);
ret = wfx_write32(wdev, WFX_REG_BASE_ADDR, addr);
if (ret < 0)
goto err;
ret = read32(wdev, WFX_REG_CONFIG, &cfg);
ret = wfx_read32(wdev, WFX_REG_CONFIG, &cfg);
if (ret < 0)
goto err;
ret = write32(wdev, WFX_REG_CONFIG, cfg | prefetch);
ret = wfx_write32(wdev, WFX_REG_CONFIG, cfg | prefetch);
if (ret < 0)
goto err;
for (i = 0; i < 20; i++) {
ret = read32(wdev, WFX_REG_CONFIG, &cfg);
ret = wfx_read32(wdev, WFX_REG_CONFIG, &cfg);
if (ret < 0)
goto err;
if (!(cfg & prefetch))
@ -148,46 +149,46 @@ err:
return ret;
}
static int indirect_write(struct wfx_dev *wdev, int reg, u32 addr,
const void *buf, size_t len)
static int wfx_indirect_write(struct wfx_dev *wdev, int reg, u32 addr,
const void *buf, size_t len)
{
int ret;
WARN_ON(len >= WFX_HIF_BUFFER_SIZE);
WARN_ON(reg != WFX_REG_AHB_DPORT && reg != WFX_REG_SRAM_DPORT);
ret = write32(wdev, WFX_REG_BASE_ADDR, addr);
ret = wfx_write32(wdev, WFX_REG_BASE_ADDR, addr);
if (ret < 0)
return ret;
return wdev->hwbus_ops->copy_to_io(wdev->hwbus_priv, reg, buf, len);
}
static int indirect_read_locked(struct wfx_dev *wdev, int reg, u32 addr,
void *buf, size_t len)
static int wfx_indirect_read_locked(struct wfx_dev *wdev, int reg, u32 addr,
void *buf, size_t len)
{
int ret;
wdev->hwbus_ops->lock(wdev->hwbus_priv);
ret = indirect_read(wdev, reg, addr, buf, len);
ret = wfx_indirect_read(wdev, reg, addr, buf, len);
_trace_io_ind_read(reg, addr, buf, len);
wdev->hwbus_ops->unlock(wdev->hwbus_priv);
return ret;
}
static int indirect_write_locked(struct wfx_dev *wdev, int reg, u32 addr,
const void *buf, size_t len)
static int wfx_indirect_write_locked(struct wfx_dev *wdev, int reg, u32 addr,
const void *buf, size_t len)
{
int ret;
wdev->hwbus_ops->lock(wdev->hwbus_priv);
ret = indirect_write(wdev, reg, addr, buf, len);
ret = wfx_indirect_write(wdev, reg, addr, buf, len);
_trace_io_ind_write(reg, addr, buf, len);
wdev->hwbus_ops->unlock(wdev->hwbus_priv);
return ret;
}
static int indirect_read32_locked(struct wfx_dev *wdev, int reg,
u32 addr, u32 *val)
static int wfx_indirect_read32_locked(struct wfx_dev *wdev, int reg,
u32 addr, u32 *val)
{
int ret;
__le32 *tmp = kmalloc(sizeof(u32), GFP_KERNEL);
@ -195,7 +196,7 @@ static int indirect_read32_locked(struct wfx_dev *wdev, int reg,
if (!tmp)
return -ENOMEM;
wdev->hwbus_ops->lock(wdev->hwbus_priv);
ret = indirect_read(wdev, reg, addr, tmp, sizeof(u32));
ret = wfx_indirect_read(wdev, reg, addr, tmp, sizeof(u32));
*val = le32_to_cpu(*tmp);
_trace_io_ind_read32(reg, addr, *val);
wdev->hwbus_ops->unlock(wdev->hwbus_priv);
@ -203,8 +204,8 @@ static int indirect_read32_locked(struct wfx_dev *wdev, int reg,
return ret;
}
static int indirect_write32_locked(struct wfx_dev *wdev, int reg,
u32 addr, u32 val)
static int wfx_indirect_write32_locked(struct wfx_dev *wdev, int reg,
u32 addr, u32 val)
{
int ret;
__le32 *tmp = kmalloc(sizeof(u32), GFP_KERNEL);
@ -213,7 +214,7 @@ static int indirect_write32_locked(struct wfx_dev *wdev, int reg,
return -ENOMEM;
*tmp = cpu_to_le32(val);
wdev->hwbus_ops->lock(wdev->hwbus_priv);
ret = indirect_write(wdev, reg, addr, tmp, sizeof(u32));
ret = wfx_indirect_write(wdev, reg, addr, tmp, sizeof(u32));
_trace_io_ind_write32(reg, addr, val);
wdev->hwbus_ops->unlock(wdev->hwbus_priv);
kfree(tmp);
@ -252,92 +253,100 @@ int wfx_data_write(struct wfx_dev *wdev, const void *buf, size_t len)
return ret;
}
int sram_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len)
int wfx_sram_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len)
{
return indirect_read_locked(wdev, WFX_REG_SRAM_DPORT, addr, buf, len);
return wfx_indirect_read_locked(wdev, WFX_REG_SRAM_DPORT,
addr, buf, len);
}
int ahb_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len)
int wfx_ahb_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len)
{
return indirect_read_locked(wdev, WFX_REG_AHB_DPORT, addr, buf, len);
return wfx_indirect_read_locked(wdev, WFX_REG_AHB_DPORT,
addr, buf, len);
}
int sram_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len)
int wfx_sram_buf_write(struct wfx_dev *wdev, u32 addr,
const void *buf, size_t len)
{
return indirect_write_locked(wdev, WFX_REG_SRAM_DPORT, addr, buf, len);
return wfx_indirect_write_locked(wdev, WFX_REG_SRAM_DPORT,
addr, buf, len);
}
int ahb_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len)
int wfx_ahb_buf_write(struct wfx_dev *wdev, u32 addr,
const void *buf, size_t len)
{
return indirect_write_locked(wdev, WFX_REG_AHB_DPORT, addr, buf, len);
return wfx_indirect_write_locked(wdev, WFX_REG_AHB_DPORT,
addr, buf, len);
}
int sram_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val)
int wfx_sram_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val)
{
return indirect_read32_locked(wdev, WFX_REG_SRAM_DPORT, addr, val);
return wfx_indirect_read32_locked(wdev, WFX_REG_SRAM_DPORT,
addr, val);
}
int ahb_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val)
int wfx_ahb_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val)
{
return indirect_read32_locked(wdev, WFX_REG_AHB_DPORT, addr, val);
return wfx_indirect_read32_locked(wdev, WFX_REG_AHB_DPORT,
addr, val);
}
int sram_reg_write(struct wfx_dev *wdev, u32 addr, u32 val)
int wfx_sram_reg_write(struct wfx_dev *wdev, u32 addr, u32 val)
{
return indirect_write32_locked(wdev, WFX_REG_SRAM_DPORT, addr, val);
return wfx_indirect_write32_locked(wdev, WFX_REG_SRAM_DPORT, addr, val);
}
int ahb_reg_write(struct wfx_dev *wdev, u32 addr, u32 val)
int wfx_ahb_reg_write(struct wfx_dev *wdev, u32 addr, u32 val)
{
return indirect_write32_locked(wdev, WFX_REG_AHB_DPORT, addr, val);
return wfx_indirect_write32_locked(wdev, WFX_REG_AHB_DPORT, addr, val);
}
int config_reg_read(struct wfx_dev *wdev, u32 *val)
int wfx_config_reg_read(struct wfx_dev *wdev, u32 *val)
{
return read32_locked(wdev, WFX_REG_CONFIG, val);
return wfx_read32_locked(wdev, WFX_REG_CONFIG, val);
}
int config_reg_write(struct wfx_dev *wdev, u32 val)
int wfx_config_reg_write(struct wfx_dev *wdev, u32 val)
{
return write32_locked(wdev, WFX_REG_CONFIG, val);
return wfx_write32_locked(wdev, WFX_REG_CONFIG, val);
}
int config_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val)
int wfx_config_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val)
{
return write32_bits_locked(wdev, WFX_REG_CONFIG, mask, val);
return wfx_write32_bits_locked(wdev, WFX_REG_CONFIG, mask, val);
}
int control_reg_read(struct wfx_dev *wdev, u32 *val)
int wfx_control_reg_read(struct wfx_dev *wdev, u32 *val)
{
return read32_locked(wdev, WFX_REG_CONTROL, val);
return wfx_read32_locked(wdev, WFX_REG_CONTROL, val);
}
int control_reg_write(struct wfx_dev *wdev, u32 val)
int wfx_control_reg_write(struct wfx_dev *wdev, u32 val)
{
return write32_locked(wdev, WFX_REG_CONTROL, val);
return wfx_write32_locked(wdev, WFX_REG_CONTROL, val);
}
int control_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val)
int wfx_control_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val)
{
return write32_bits_locked(wdev, WFX_REG_CONTROL, mask, val);
return wfx_write32_bits_locked(wdev, WFX_REG_CONTROL, mask, val);
}
int igpr_reg_read(struct wfx_dev *wdev, int index, u32 *val)
int wfx_igpr_reg_read(struct wfx_dev *wdev, int index, u32 *val)
{
int ret;
*val = ~0; /* Never return undefined value */
ret = write32_locked(wdev, WFX_REG_SET_GEN_R_W, IGPR_RW | index << 24);
ret = wfx_write32_locked(wdev, WFX_REG_SET_GEN_R_W, IGPR_RW | index << 24);
if (ret)
return ret;
ret = read32_locked(wdev, WFX_REG_SET_GEN_R_W, val);
ret = wfx_read32_locked(wdev, WFX_REG_SET_GEN_R_W, val);
if (ret)
return ret;
*val &= IGPR_VALUE;
return ret;
}
int igpr_reg_write(struct wfx_dev *wdev, int index, u32 val)
int wfx_igpr_reg_write(struct wfx_dev *wdev, int index, u32 val)
{
return write32_locked(wdev, WFX_REG_SET_GEN_R_W, index << 24 | val);
return wfx_write32_locked(wdev, WFX_REG_SET_GEN_R_W, index << 24 | val);
}

32
drivers/staging/wfx/hwio.h
Просмотреть файл

@ -19,17 +19,17 @@ struct wfx_dev;
int wfx_data_read(struct wfx_dev *wdev, void *buf, size_t buf_len);
int wfx_data_write(struct wfx_dev *wdev, const void *buf, size_t buf_len);
int sram_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len);
int sram_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len);
int wfx_sram_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len);
int wfx_sram_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len);
int ahb_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len);
int ahb_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len);
int wfx_ahb_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len);
int wfx_ahb_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len);
int sram_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val);
int sram_reg_write(struct wfx_dev *wdev, u32 addr, u32 val);
int wfx_sram_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val);
int wfx_sram_reg_write(struct wfx_dev *wdev, u32 addr, u32 val);
int ahb_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val);
int ahb_reg_write(struct wfx_dev *wdev, u32 addr, u32 val);
int wfx_ahb_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val);
int wfx_ahb_reg_write(struct wfx_dev *wdev, u32 addr, u32 val);
#define CFG_ERR_SPI_FRAME 0x00000001 /* only with SPI */
#define CFG_ERR_SDIO_BUF_MISMATCH 0x00000001 /* only with SDIO */
@ -59,21 +59,21 @@ int ahb_reg_write(struct wfx_dev *wdev, u32 addr, u32 val);
#define CFG_DEVICE_ID_MAJOR 0x07000000
#define CFG_DEVICE_ID_RESERVED 0x78000000
#define CFG_DEVICE_ID_TYPE 0x80000000
int config_reg_read(struct wfx_dev *wdev, u32 *val);
int config_reg_write(struct wfx_dev *wdev, u32 val);
int config_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val);
int wfx_config_reg_read(struct wfx_dev *wdev, u32 *val);
int wfx_config_reg_write(struct wfx_dev *wdev, u32 val);
int wfx_config_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val);
#define CTRL_NEXT_LEN_MASK 0x00000FFF
#define CTRL_WLAN_WAKEUP 0x00001000
#define CTRL_WLAN_READY 0x00002000
int control_reg_read(struct wfx_dev *wdev, u32 *val);
int control_reg_write(struct wfx_dev *wdev, u32 val);
int control_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val);
int wfx_control_reg_read(struct wfx_dev *wdev, u32 *val);
int wfx_control_reg_write(struct wfx_dev *wdev, u32 val);
int wfx_control_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val);
#define IGPR_RW 0x80000000
#define IGPR_INDEX 0x7F000000
#define IGPR_VALUE 0x00FFFFFF
int igpr_reg_read(struct wfx_dev *wdev, int index, u32 *val);
int igpr_reg_write(struct wfx_dev *wdev, int index, u32 val);
int wfx_igpr_reg_read(struct wfx_dev *wdev, int index, u32 *val);
int wfx_igpr_reg_write(struct wfx_dev *wdev, int index, u32 val);
#endif

2
drivers/staging/wfx/main.c
Просмотреть файл

@ -428,7 +428,7 @@ int wfx_probe(struct wfx_dev *wdev)
"enable 'quiescent' power mode with wakeup GPIO and PDS file %s\n",
wdev->pdata.file_pds);
gpiod_set_value_cansleep(wdev->pdata.gpio_wakeup, 1);
control_reg_write(wdev, 0);
wfx_control_reg_write(wdev, 0);
wfx_hif_set_operational_mode(wdev, HIF_OP_POWER_MODE_QUIESCENT);
} else {
wfx_hif_set_operational_mode(wdev, HIF_OP_POWER_MODE_DOZE);