phy: mediatek: add XS-PHY driver
Support XS-PHY for MediaTek SoCs with USB3.1 GEN2 controller Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Chunfeng Yun
Kishon Vijay Abraham I
Родитель
ebd52733e9
Коммит
c1eb8f8384
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@ -12,3 +12,12 @@ config PHY_MTK_TPHY
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different banks layout, the T-PHY with shared banks between
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multi-ports is first version, otherwise is second veriosn,
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so you can easily distinguish them by banks layout.
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config PHY_MTK_XSPHY
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tristate "MediaTek XS-PHY Driver"
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depends on ARCH_MEDIATEK && OF
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select GENERIC_PHY
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help
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Enable this to support the SuperSpeedPlus XS-PHY transceiver for
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USB3.1 GEN2 controllers on MediaTek chips. The driver supports
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multiple USB2.0, USB3.1 GEN2 ports.
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@ -3,3 +3,4 @@
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#
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obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o
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obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o
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@ -0,0 +1,600 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* MediaTek USB3.1 gen2 xsphy Driver
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*
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* Copyright (c) 2018 MediaTek Inc.
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* Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
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*
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*/
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#include <dt-bindings/phy/phy.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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/* u2 phy banks */
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#define SSUSB_SIFSLV_MISC 0x000
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#define SSUSB_SIFSLV_U2FREQ 0x100
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#define SSUSB_SIFSLV_U2PHY_COM 0x300
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/* u3 phy shared banks */
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#define SSPXTP_SIFSLV_DIG_GLB 0x000
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#define SSPXTP_SIFSLV_PHYA_GLB 0x100
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/* u3 phy banks */
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#define SSPXTP_SIFSLV_DIG_LN_TOP 0x000
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#define SSPXTP_SIFSLV_DIG_LN_TX0 0x100
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#define SSPXTP_SIFSLV_DIG_LN_RX0 0x200
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#define SSPXTP_SIFSLV_DIG_LN_DAIF 0x300
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#define SSPXTP_SIFSLV_PHYA_LN 0x400
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#define XSP_U2FREQ_FMCR0 ((SSUSB_SIFSLV_U2FREQ) + 0x00)
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#define P2F_RG_FREQDET_EN BIT(24)
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#define P2F_RG_CYCLECNT GENMASK(23, 0)
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#define P2F_RG_CYCLECNT_VAL(x) ((P2F_RG_CYCLECNT) & (x))
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#define XSP_U2FREQ_MMONR0 ((SSUSB_SIFSLV_U2FREQ) + 0x0c)
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#define XSP_U2FREQ_FMMONR1 ((SSUSB_SIFSLV_U2FREQ) + 0x10)
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#define P2F_RG_FRCK_EN BIT(8)
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#define P2F_USB_FM_VALID BIT(0)
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#define XSP_USBPHYACR0 ((SSUSB_SIFSLV_U2PHY_COM) + 0x00)
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#define P2A0_RG_INTR_EN BIT(5)
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#define XSP_USBPHYACR1 ((SSUSB_SIFSLV_U2PHY_COM) + 0x04)
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#define P2A1_RG_INTR_CAL GENMASK(23, 19)
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#define P2A1_RG_INTR_CAL_VAL(x) ((0x1f & (x)) << 19)
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#define P2A1_RG_VRT_SEL GENMASK(14, 12)
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#define P2A1_RG_VRT_SEL_VAL(x) ((0x7 & (x)) << 12)
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#define P2A1_RG_TERM_SEL GENMASK(10, 8)
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#define P2A1_RG_TERM_SEL_VAL(x) ((0x7 & (x)) << 8)
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#define XSP_USBPHYACR5 ((SSUSB_SIFSLV_U2PHY_COM) + 0x014)
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#define P2A5_RG_HSTX_SRCAL_EN BIT(15)
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#define P2A5_RG_HSTX_SRCTRL GENMASK(14, 12)
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#define P2A5_RG_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12)
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#define XSP_USBPHYACR6 ((SSUSB_SIFSLV_U2PHY_COM) + 0x018)
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#define P2A6_RG_BC11_SW_EN BIT(23)
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#define P2A6_RG_OTG_VBUSCMP_EN BIT(20)
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#define XSP_U2PHYDTM1 ((SSUSB_SIFSLV_U2PHY_COM) + 0x06C)
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#define P2D_FORCE_IDDIG BIT(9)
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#define P2D_RG_VBUSVALID BIT(5)
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#define P2D_RG_SESSEND BIT(4)
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#define P2D_RG_AVALID BIT(2)
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#define P2D_RG_IDDIG BIT(1)
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#define SSPXTP_PHYA_GLB_00 ((SSPXTP_SIFSLV_PHYA_GLB) + 0x00)
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#define RG_XTP_GLB_BIAS_INTR_CTRL GENMASK(21, 16)
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#define RG_XTP_GLB_BIAS_INTR_CTRL_VAL(x) ((0x3f & (x)) << 16)
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#define SSPXTP_PHYA_LN_04 ((SSPXTP_SIFSLV_PHYA_LN) + 0x04)
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#define RG_XTP_LN0_TX_IMPSEL GENMASK(4, 0)
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#define RG_XTP_LN0_TX_IMPSEL_VAL(x) (0x1f & (x))
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#define SSPXTP_PHYA_LN_14 ((SSPXTP_SIFSLV_PHYA_LN) + 0x014)
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#define RG_XTP_LN0_RX_IMPSEL GENMASK(4, 0)
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#define RG_XTP_LN0_RX_IMPSEL_VAL(x) (0x1f & (x))
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#define XSP_REF_CLK 26 /* MHZ */
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#define XSP_SLEW_RATE_COEF 17
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#define XSP_SR_COEF_DIVISOR 1000
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#define XSP_FM_DET_CYCLE_CNT 1024
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struct xsphy_instance {
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struct phy *phy;
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void __iomem *port_base;
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struct clk *ref_clk; /* reference clock of anolog phy */
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u32 index;
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u32 type;
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/* only for HQA test */
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int efuse_intr;
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int efuse_tx_imp;
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int efuse_rx_imp;
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/* u2 eye diagram */
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int eye_src;
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int eye_vrt;
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int eye_term;
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};
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struct mtk_xsphy {
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struct device *dev;
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void __iomem *glb_base; /* only shared u3 sif */
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struct xsphy_instance **phys;
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int nphys;
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int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
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int src_coef; /* coefficient for slew rate calibrate */
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};
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static void u2_phy_slew_rate_calibrate(struct mtk_xsphy *xsphy,
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struct xsphy_instance *inst)
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{
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void __iomem *pbase = inst->port_base;
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int calib_val;
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int fm_out;
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u32 tmp;
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/* use force value */
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if (inst->eye_src)
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return;
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/* enable USB ring oscillator */
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tmp = readl(pbase + XSP_USBPHYACR5);
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tmp |= P2A5_RG_HSTX_SRCAL_EN;
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writel(tmp, pbase + XSP_USBPHYACR5);
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udelay(1); /* wait clock stable */
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/* enable free run clock */
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tmp = readl(pbase + XSP_U2FREQ_FMMONR1);
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tmp |= P2F_RG_FRCK_EN;
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writel(tmp, pbase + XSP_U2FREQ_FMMONR1);
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/* set cycle count as 1024 */
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tmp = readl(pbase + XSP_U2FREQ_FMCR0);
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tmp &= ~(P2F_RG_CYCLECNT);
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tmp |= P2F_RG_CYCLECNT_VAL(XSP_FM_DET_CYCLE_CNT);
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writel(tmp, pbase + XSP_U2FREQ_FMCR0);
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/* enable frequency meter */
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tmp = readl(pbase + XSP_U2FREQ_FMCR0);
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tmp |= P2F_RG_FREQDET_EN;
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writel(tmp, pbase + XSP_U2FREQ_FMCR0);
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/* ignore return value */
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readl_poll_timeout(pbase + XSP_U2FREQ_FMMONR1, tmp,
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(tmp & P2F_USB_FM_VALID), 10, 200);
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fm_out = readl(pbase + XSP_U2FREQ_MMONR0);
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/* disable frequency meter */
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tmp = readl(pbase + XSP_U2FREQ_FMCR0);
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tmp &= ~P2F_RG_FREQDET_EN;
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writel(tmp, pbase + XSP_U2FREQ_FMCR0);
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/* disable free run clock */
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tmp = readl(pbase + XSP_U2FREQ_FMMONR1);
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tmp &= ~P2F_RG_FRCK_EN;
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writel(tmp, pbase + XSP_U2FREQ_FMMONR1);
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if (fm_out) {
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/* (1024 / FM_OUT) x reference clock frequency x coefficient */
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tmp = xsphy->src_ref_clk * xsphy->src_coef;
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tmp = (tmp * XSP_FM_DET_CYCLE_CNT) / fm_out;
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calib_val = DIV_ROUND_CLOSEST(tmp, XSP_SR_COEF_DIVISOR);
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} else {
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/* if FM detection fail, set default value */
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calib_val = 3;
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}
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dev_dbg(xsphy->dev, "phy.%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n",
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inst->index, fm_out, calib_val,
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xsphy->src_ref_clk, xsphy->src_coef);
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/* set HS slew rate */
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tmp = readl(pbase + XSP_USBPHYACR5);
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tmp &= ~P2A5_RG_HSTX_SRCTRL;
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tmp |= P2A5_RG_HSTX_SRCTRL_VAL(calib_val);
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writel(tmp, pbase + XSP_USBPHYACR5);
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/* disable USB ring oscillator */
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tmp = readl(pbase + XSP_USBPHYACR5);
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tmp &= ~P2A5_RG_HSTX_SRCAL_EN;
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writel(tmp, pbase + XSP_USBPHYACR5);
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}
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static void u2_phy_instance_init(struct mtk_xsphy *xsphy,
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struct xsphy_instance *inst)
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{
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void __iomem *pbase = inst->port_base;
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u32 tmp;
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/* DP/DM BC1.1 path Disable */
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tmp = readl(pbase + XSP_USBPHYACR6);
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tmp &= ~P2A6_RG_BC11_SW_EN;
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writel(tmp, pbase + XSP_USBPHYACR6);
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tmp = readl(pbase + XSP_USBPHYACR0);
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tmp |= P2A0_RG_INTR_EN;
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writel(tmp, pbase + XSP_USBPHYACR0);
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}
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static void u2_phy_instance_power_on(struct mtk_xsphy *xsphy,
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struct xsphy_instance *inst)
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{
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void __iomem *pbase = inst->port_base;
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u32 index = inst->index;
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u32 tmp;
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tmp = readl(pbase + XSP_USBPHYACR6);
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tmp |= P2A6_RG_OTG_VBUSCMP_EN;
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writel(tmp, pbase + XSP_USBPHYACR6);
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tmp = readl(pbase + XSP_U2PHYDTM1);
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tmp |= P2D_RG_VBUSVALID | P2D_RG_AVALID;
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tmp &= ~P2D_RG_SESSEND;
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writel(tmp, pbase + XSP_U2PHYDTM1);
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dev_dbg(xsphy->dev, "%s(%d)\n", __func__, index);
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}
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static void u2_phy_instance_power_off(struct mtk_xsphy *xsphy,
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struct xsphy_instance *inst)
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{
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void __iomem *pbase = inst->port_base;
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u32 index = inst->index;
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u32 tmp;
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tmp = readl(pbase + XSP_USBPHYACR6);
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tmp &= ~P2A6_RG_OTG_VBUSCMP_EN;
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writel(tmp, pbase + XSP_USBPHYACR6);
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tmp = readl(pbase + XSP_U2PHYDTM1);
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tmp &= ~(P2D_RG_VBUSVALID | P2D_RG_AVALID);
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tmp |= P2D_RG_SESSEND;
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writel(tmp, pbase + XSP_U2PHYDTM1);
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dev_dbg(xsphy->dev, "%s(%d)\n", __func__, index);
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}
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static void u2_phy_instance_set_mode(struct mtk_xsphy *xsphy,
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struct xsphy_instance *inst,
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enum phy_mode mode)
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{
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u32 tmp;
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tmp = readl(inst->port_base + XSP_U2PHYDTM1);
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switch (mode) {
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case PHY_MODE_USB_DEVICE:
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tmp |= P2D_FORCE_IDDIG | P2D_RG_IDDIG;
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break;
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case PHY_MODE_USB_HOST:
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tmp |= P2D_FORCE_IDDIG;
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tmp &= ~P2D_RG_IDDIG;
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break;
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case PHY_MODE_USB_OTG:
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tmp &= ~(P2D_FORCE_IDDIG | P2D_RG_IDDIG);
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break;
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default:
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return;
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}
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writel(tmp, inst->port_base + XSP_U2PHYDTM1);
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}
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static void phy_parse_property(struct mtk_xsphy *xsphy,
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struct xsphy_instance *inst)
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{
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struct device *dev = &inst->phy->dev;
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switch (inst->type) {
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case PHY_TYPE_USB2:
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device_property_read_u32(dev, "mediatek,efuse-intr",
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&inst->efuse_intr);
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device_property_read_u32(dev, "mediatek,eye-src",
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&inst->eye_src);
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device_property_read_u32(dev, "mediatek,eye-vrt",
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&inst->eye_vrt);
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device_property_read_u32(dev, "mediatek,eye-term",
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&inst->eye_term);
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dev_dbg(dev, "intr:%d, src:%d, vrt:%d, term:%d\n",
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inst->efuse_intr, inst->eye_src,
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inst->eye_vrt, inst->eye_term);
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break;
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case PHY_TYPE_USB3:
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device_property_read_u32(dev, "mediatek,efuse-intr",
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&inst->efuse_intr);
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device_property_read_u32(dev, "mediatek,efuse-tx-imp",
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&inst->efuse_tx_imp);
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device_property_read_u32(dev, "mediatek,efuse-rx-imp",
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&inst->efuse_rx_imp);
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dev_dbg(dev, "intr:%d, tx-imp:%d, rx-imp:%d\n",
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inst->efuse_intr, inst->efuse_tx_imp,
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inst->efuse_rx_imp);
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break;
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default:
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dev_err(xsphy->dev, "incompatible phy type\n");
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return;
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}
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}
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static void u2_phy_props_set(struct mtk_xsphy *xsphy,
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struct xsphy_instance *inst)
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{
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void __iomem *pbase = inst->port_base;
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u32 tmp;
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if (inst->efuse_intr) {
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tmp = readl(pbase + XSP_USBPHYACR1);
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tmp &= ~P2A1_RG_INTR_CAL;
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tmp |= P2A1_RG_INTR_CAL_VAL(inst->efuse_intr);
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writel(tmp, pbase + XSP_USBPHYACR1);
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}
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if (inst->eye_src) {
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tmp = readl(pbase + XSP_USBPHYACR5);
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tmp &= ~P2A5_RG_HSTX_SRCTRL;
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tmp |= P2A5_RG_HSTX_SRCTRL_VAL(inst->eye_src);
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writel(tmp, pbase + XSP_USBPHYACR5);
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}
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if (inst->eye_vrt) {
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tmp = readl(pbase + XSP_USBPHYACR1);
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tmp &= ~P2A1_RG_VRT_SEL;
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tmp |= P2A1_RG_VRT_SEL_VAL(inst->eye_vrt);
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writel(tmp, pbase + XSP_USBPHYACR1);
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}
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if (inst->eye_term) {
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tmp = readl(pbase + XSP_USBPHYACR1);
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tmp &= ~P2A1_RG_TERM_SEL;
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tmp |= P2A1_RG_TERM_SEL_VAL(inst->eye_term);
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writel(tmp, pbase + XSP_USBPHYACR1);
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}
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}
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static void u3_phy_props_set(struct mtk_xsphy *xsphy,
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struct xsphy_instance *inst)
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{
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void __iomem *pbase = inst->port_base;
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u32 tmp;
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if (inst->efuse_intr) {
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tmp = readl(xsphy->glb_base + SSPXTP_PHYA_GLB_00);
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tmp &= ~RG_XTP_GLB_BIAS_INTR_CTRL;
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tmp |= RG_XTP_GLB_BIAS_INTR_CTRL_VAL(inst->efuse_intr);
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writel(tmp, xsphy->glb_base + SSPXTP_PHYA_GLB_00);
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}
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if (inst->efuse_tx_imp) {
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tmp = readl(pbase + SSPXTP_PHYA_LN_04);
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tmp &= ~RG_XTP_LN0_TX_IMPSEL;
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tmp |= RG_XTP_LN0_TX_IMPSEL_VAL(inst->efuse_tx_imp);
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writel(tmp, pbase + SSPXTP_PHYA_LN_04);
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}
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if (inst->efuse_rx_imp) {
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tmp = readl(pbase + SSPXTP_PHYA_LN_14);
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tmp &= ~RG_XTP_LN0_RX_IMPSEL;
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tmp |= RG_XTP_LN0_RX_IMPSEL_VAL(inst->efuse_rx_imp);
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writel(tmp, pbase + SSPXTP_PHYA_LN_14);
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}
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}
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static int mtk_phy_init(struct phy *phy)
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{
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struct xsphy_instance *inst = phy_get_drvdata(phy);
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struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);
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int ret;
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ret = clk_prepare_enable(inst->ref_clk);
|
||||
if (ret) {
|
||||
dev_err(xsphy->dev, "failed to enable ref_clk\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
switch (inst->type) {
|
||||
case PHY_TYPE_USB2:
|
||||
u2_phy_instance_init(xsphy, inst);
|
||||
u2_phy_props_set(xsphy, inst);
|
||||
break;
|
||||
case PHY_TYPE_USB3:
|
||||
u3_phy_props_set(xsphy, inst);
|
||||
break;
|
||||
default:
|
||||
dev_err(xsphy->dev, "incompatible phy type\n");
|
||||
clk_disable_unprepare(inst->ref_clk);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_phy_power_on(struct phy *phy)
|
||||
{
|
||||
struct xsphy_instance *inst = phy_get_drvdata(phy);
|
||||
struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);
|
||||
|
||||
if (inst->type == PHY_TYPE_USB2) {
|
||||
u2_phy_instance_power_on(xsphy, inst);
|
||||
u2_phy_slew_rate_calibrate(xsphy, inst);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_phy_power_off(struct phy *phy)
|
||||
{
|
||||
struct xsphy_instance *inst = phy_get_drvdata(phy);
|
||||
struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);
|
||||
|
||||
if (inst->type == PHY_TYPE_USB2)
|
||||
u2_phy_instance_power_off(xsphy, inst);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_phy_exit(struct phy *phy)
|
||||
{
|
||||
struct xsphy_instance *inst = phy_get_drvdata(phy);
|
||||
|
||||
clk_disable_unprepare(inst->ref_clk);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode)
|
||||
{
|
||||
struct xsphy_instance *inst = phy_get_drvdata(phy);
|
||||
struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);
|
||||
|
||||
if (inst->type == PHY_TYPE_USB2)
|
||||
u2_phy_instance_set_mode(xsphy, inst, mode);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct phy *mtk_phy_xlate(struct device *dev,
|
||||
struct of_phandle_args *args)
|
||||
{
|
||||
struct mtk_xsphy *xsphy = dev_get_drvdata(dev);
|
||||
struct xsphy_instance *inst = NULL;
|
||||
struct device_node *phy_np = args->np;
|
||||
int index;
|
||||
|
||||
if (args->args_count != 1) {
|
||||
dev_err(dev, "invalid number of cells in 'phy' property\n");
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
for (index = 0; index < xsphy->nphys; index++)
|
||||
if (phy_np == xsphy->phys[index]->phy->dev.of_node) {
|
||||
inst = xsphy->phys[index];
|
||||
break;
|
||||
}
|
||||
|
||||
if (!inst) {
|
||||
dev_err(dev, "failed to find appropriate phy\n");
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
inst->type = args->args[0];
|
||||
if (!(inst->type == PHY_TYPE_USB2 ||
|
||||
inst->type == PHY_TYPE_USB3)) {
|
||||
dev_err(dev, "unsupported phy type: %d\n", inst->type);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
phy_parse_property(xsphy, inst);
|
||||
|
||||
return inst->phy;
|
||||
}
|
||||
|
||||
static const struct phy_ops mtk_xsphy_ops = {
|
||||
.init = mtk_phy_init,
|
||||
.exit = mtk_phy_exit,
|
||||
.power_on = mtk_phy_power_on,
|
||||
.power_off = mtk_phy_power_off,
|
||||
.set_mode = mtk_phy_set_mode,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
static const struct of_device_id mtk_xsphy_id_table[] = {
|
||||
{ .compatible = "mediatek,xsphy", },
|
||||
{ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mtk_xsphy_id_table);
|
||||
|
||||
static int mtk_xsphy_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct device_node *child_np;
|
||||
struct phy_provider *provider;
|
||||
struct resource *glb_res;
|
||||
struct mtk_xsphy *xsphy;
|
||||
struct resource res;
|
||||
int port, retval;
|
||||
|
||||
xsphy = devm_kzalloc(dev, sizeof(*xsphy), GFP_KERNEL);
|
||||
if (!xsphy)
|
||||
return -ENOMEM;
|
||||
|
||||
xsphy->nphys = of_get_child_count(np);
|
||||
xsphy->phys = devm_kcalloc(dev, xsphy->nphys,
|
||||
sizeof(*xsphy->phys), GFP_KERNEL);
|
||||
if (!xsphy->phys)
|
||||
return -ENOMEM;
|
||||
|
||||
xsphy->dev = dev;
|
||||
platform_set_drvdata(pdev, xsphy);
|
||||
|
||||
glb_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
/* optional, may not exist if no u3 phys */
|
||||
if (glb_res) {
|
||||
/* get banks shared by multiple u3 phys */
|
||||
xsphy->glb_base = devm_ioremap_resource(dev, glb_res);
|
||||
if (IS_ERR(xsphy->glb_base)) {
|
||||
dev_err(dev, "failed to remap glb regs\n");
|
||||
return PTR_ERR(xsphy->glb_base);
|
||||
}
|
||||
}
|
||||
|
||||
xsphy->src_ref_clk = XSP_REF_CLK;
|
||||
xsphy->src_coef = XSP_SLEW_RATE_COEF;
|
||||
/* update parameters of slew rate calibrate if exist */
|
||||
device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
|
||||
&xsphy->src_ref_clk);
|
||||
device_property_read_u32(dev, "mediatek,src-coef", &xsphy->src_coef);
|
||||
|
||||
port = 0;
|
||||
for_each_child_of_node(np, child_np) {
|
||||
struct xsphy_instance *inst;
|
||||
struct phy *phy;
|
||||
|
||||
inst = devm_kzalloc(dev, sizeof(*inst), GFP_KERNEL);
|
||||
if (!inst) {
|
||||
retval = -ENOMEM;
|
||||
goto put_child;
|
||||
}
|
||||
|
||||
xsphy->phys[port] = inst;
|
||||
|
||||
phy = devm_phy_create(dev, child_np, &mtk_xsphy_ops);
|
||||
if (IS_ERR(phy)) {
|
||||
dev_err(dev, "failed to create phy\n");
|
||||
retval = PTR_ERR(phy);
|
||||
goto put_child;
|
||||
}
|
||||
|
||||
retval = of_address_to_resource(child_np, 0, &res);
|
||||
if (retval) {
|
||||
dev_err(dev, "failed to get address resource(id-%d)\n",
|
||||
port);
|
||||
goto put_child;
|
||||
}
|
||||
|
||||
inst->port_base = devm_ioremap_resource(&phy->dev, &res);
|
||||
if (IS_ERR(inst->port_base)) {
|
||||
dev_err(dev, "failed to remap phy regs\n");
|
||||
retval = PTR_ERR(inst->port_base);
|
||||
goto put_child;
|
||||
}
|
||||
|
||||
inst->phy = phy;
|
||||
inst->index = port;
|
||||
phy_set_drvdata(phy, inst);
|
||||
port++;
|
||||
|
||||
inst->ref_clk = devm_clk_get(&phy->dev, "ref");
|
||||
if (IS_ERR(inst->ref_clk)) {
|
||||
dev_err(dev, "failed to get ref_clk(id-%d)\n", port);
|
||||
retval = PTR_ERR(inst->ref_clk);
|
||||
goto put_child;
|
||||
}
|
||||
}
|
||||
|
||||
provider = devm_of_phy_provider_register(dev, mtk_phy_xlate);
|
||||
return PTR_ERR_OR_ZERO(provider);
|
||||
|
||||
put_child:
|
||||
of_node_put(child_np);
|
||||
return retval;
|
||||
}
|
||||
|
||||
static struct platform_driver mtk_xsphy_driver = {
|
||||
.probe = mtk_xsphy_probe,
|
||||
.driver = {
|
||||
.name = "mtk-xsphy",
|
||||
.of_match_table = mtk_xsphy_id_table,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(mtk_xsphy_driver);
|
||||
|
||||
MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
|
||||
MODULE_DESCRIPTION("MediaTek USB XS-PHY driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Загрузка…
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