drm/nouveau/bios/ramcfg: Separate out RON pull value
Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Родитель
2813e19f13
Коммит
c25bf7b615
|
@ -38,6 +38,7 @@ struct nvbios_ramcfg {
|
||||||
unsigned ramcfg_hdr;
|
unsigned ramcfg_hdr;
|
||||||
unsigned ramcfg_timing;
|
unsigned ramcfg_timing;
|
||||||
unsigned ramcfg_DLLoff;
|
unsigned ramcfg_DLLoff;
|
||||||
|
unsigned ramcfg_RON;
|
||||||
union {
|
union {
|
||||||
struct {
|
struct {
|
||||||
unsigned ramcfg_00_03_01:1;
|
unsigned ramcfg_00_03_01:1;
|
||||||
|
|
|
@ -164,12 +164,13 @@ nvbios_rammapSp_from_perf(struct nvkm_bios *bios, u32 data, u8 size, int idx,
|
||||||
if (size < 11)
|
if (size < 11)
|
||||||
return 0x00000000;
|
return 0x00000000;
|
||||||
|
|
||||||
|
p->ramcfg_ver = 0;
|
||||||
p->ramcfg_timing = nv_ro08(bios, data + 0x01);
|
p->ramcfg_timing = nv_ro08(bios, data + 0x01);
|
||||||
p->ramcfg_00_03_01 = (nv_ro08(bios, data + 0x03) & 0x01) >> 0;
|
p->ramcfg_00_03_01 = (nv_ro08(bios, data + 0x03) & 0x01) >> 0;
|
||||||
p->ramcfg_00_03_02 = (nv_ro08(bios, data + 0x03) & 0x02) >> 1;
|
p->ramcfg_00_03_02 = (nv_ro08(bios, data + 0x03) & 0x02) >> 1;
|
||||||
p->ramcfg_DLLoff = (nv_ro08(bios, data + 0x03) & 0x04) >> 2;
|
p->ramcfg_DLLoff = (nv_ro08(bios, data + 0x03) & 0x04) >> 2;
|
||||||
p->ramcfg_00_03_08 = (nv_ro08(bios, data + 0x03) & 0x08) >> 3;
|
p->ramcfg_00_03_08 = (nv_ro08(bios, data + 0x03) & 0x08) >> 3;
|
||||||
p->ramcfg_00_03_10 = (nv_ro08(bios, data + 0x03) & 0x10) >> 4;
|
p->ramcfg_RON = (nv_ro08(bios, data + 0x03) & 0x10) >> 3;
|
||||||
p->ramcfg_00_04_02 = (nv_ro08(bios, data + 0x04) & 0x02) >> 1;
|
p->ramcfg_00_04_02 = (nv_ro08(bios, data + 0x04) & 0x02) >> 1;
|
||||||
p->ramcfg_00_04_04 = (nv_ro08(bios, data + 0x04) & 0x04) >> 2;
|
p->ramcfg_00_04_04 = (nv_ro08(bios, data + 0x04) & 0x04) >> 2;
|
||||||
p->ramcfg_00_04_20 = (nv_ro08(bios, data + 0x04) & 0x20) >> 5;
|
p->ramcfg_00_04_20 = (nv_ro08(bios, data + 0x04) & 0x20) >> 5;
|
||||||
|
|
|
@ -102,6 +102,8 @@ nvbios_timingEp(struct nvkm_bios *bios, int idx,
|
||||||
p->timing_10_RRD = nv_ro08(bios, data + 0x0c);
|
p->timing_10_RRD = nv_ro08(bios, data + 0x0c);
|
||||||
p->timing_10_13 = nv_ro08(bios, data + 0x0d);
|
p->timing_10_13 = nv_ro08(bios, data + 0x0d);
|
||||||
p->timing_10_ODT = nv_ro08(bios, data + 0x0e) & 0x07;
|
p->timing_10_ODT = nv_ro08(bios, data + 0x0e) & 0x07;
|
||||||
|
if (p->ramcfg_ver >= 0x10)
|
||||||
|
p->ramcfg_RON = nv_ro08(bios, data + 0x0e) & 0x07;
|
||||||
|
|
||||||
p->timing_10_24 = 0xff;
|
p->timing_10_24 = 0xff;
|
||||||
p->timing_10_21 = 0;
|
p->timing_10_21 = 0;
|
||||||
|
|
|
@ -70,7 +70,7 @@ ramgddr3_wr_lo[] = {
|
||||||
int
|
int
|
||||||
nvkm_gddr3_calc(struct nvkm_ram *ram)
|
nvkm_gddr3_calc(struct nvkm_ram *ram)
|
||||||
{
|
{
|
||||||
int CL, WR, CWL, DLL = 0, ODT = 0, hi;
|
int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi;
|
||||||
|
|
||||||
switch (ram->next->bios.timing_ver) {
|
switch (ram->next->bios.timing_ver) {
|
||||||
case 0x10:
|
case 0x10:
|
||||||
|
@ -79,6 +79,7 @@ nvkm_gddr3_calc(struct nvkm_ram *ram)
|
||||||
WR = ram->next->bios.timing_10_WR;
|
WR = ram->next->bios.timing_10_WR;
|
||||||
DLL = !ram->next->bios.ramcfg_DLLoff;
|
DLL = !ram->next->bios.ramcfg_DLLoff;
|
||||||
ODT = ram->next->bios.timing_10_ODT;
|
ODT = ram->next->bios.timing_10_ODT;
|
||||||
|
RON = ram->next->bios.ramcfg_RON;
|
||||||
break;
|
break;
|
||||||
case 0x20:
|
case 0x20:
|
||||||
CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
|
CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
|
||||||
|
@ -89,6 +90,7 @@ nvkm_gddr3_calc(struct nvkm_ram *ram)
|
||||||
ODT = (ram->mr[1] & 0x004) >> 2 |
|
ODT = (ram->mr[1] & 0x004) >> 2 |
|
||||||
(ram->mr[1] & 0x040) >> 5 |
|
(ram->mr[1] & 0x040) >> 5 |
|
||||||
(ram->mr[1] & 0x200) >> 7;
|
(ram->mr[1] & 0x200) >> 7;
|
||||||
|
RON = !(ram->mr[1] & 0x300) >> 8;
|
||||||
break;
|
break;
|
||||||
default:
|
default:
|
||||||
return -ENOSYS;
|
return -ENOSYS;
|
||||||
|
@ -107,7 +109,7 @@ nvkm_gddr3_calc(struct nvkm_ram *ram)
|
||||||
|
|
||||||
ram->mr[1] &= ~0x3fc;
|
ram->mr[1] &= ~0x3fc;
|
||||||
ram->mr[1] |= (ODT & 0x03) << 2;
|
ram->mr[1] |= (ODT & 0x03) << 2;
|
||||||
ram->mr[1] |= (ODT & 0x03) << 8;
|
ram->mr[1] |= (RON & 0x03) << 8;
|
||||||
ram->mr[1] |= (WR & 0x03) << 4;
|
ram->mr[1] |= (WR & 0x03) << 4;
|
||||||
ram->mr[1] |= (WR & 0x04) << 5;
|
ram->mr[1] |= (WR & 0x04) << 5;
|
||||||
ram->mr[1] |= !DLL << 6;
|
ram->mr[1] |= !DLL << 6;
|
||||||
|
|
Загрузка…
Ссылка в новой задаче