powerpc/code-patching: Use temporary mm for Radix MMU
x86 supports the notion of a temporary mm which restricts access to temporary PTEs to a single CPU. A temporary mm is useful for situations where a CPU needs to perform sensitive operations (such as patching a STRICT_KERNEL_RWX kernel) requiring temporary mappings without exposing said mappings to other CPUs. Another benefit is that other CPU TLBs do not need to be flushed when the temporary mm is torn down. Mappings in the temporary mm can be set in the userspace portion of the address-space. Interrupts must be disabled while the temporary mm is in use. HW breakpoints, which may have been set by userspace as watchpoints on addresses now within the temporary mm, are saved and disabled when loading the temporary mm. The HW breakpoints are restored when unloading the temporary mm. All HW breakpoints are indiscriminately disabled while the temporary mm is in use - this may include breakpoints set by perf. Use the `poking_init` init hook to prepare a temporary mm and patching address. Initialize the temporary mm using mm_alloc(). Choose a randomized patching address inside the temporary mm userspace address space. The patching address is randomized between PAGE_SIZE and DEFAULT_MAP_WINDOW-PAGE_SIZE. Bits of entropy with 64K page size on BOOK3S_64: bits of entropy = log2(DEFAULT_MAP_WINDOW_USER64 / PAGE_SIZE) PAGE_SIZE=64K, DEFAULT_MAP_WINDOW_USER64=128TB bits of entropy = log2(128TB / 64K) bits of entropy = 31 The upper limit is DEFAULT_MAP_WINDOW due to how the Book3s64 Hash MMU operates - by default the space above DEFAULT_MAP_WINDOW is not available. Currently the Hash MMU does not use a temporary mm so technically this upper limit isn't necessary; however, a larger randomization range does not further "harden" this overall approach and future work may introduce patching with a temporary mm on Hash as well. Randomization occurs only once during initialization for each CPU as it comes online. The patching page is mapped with PAGE_KERNEL to set EAA[0] for the PTE which ignores the AMR (so no need to unlock/lock KUAP) according to PowerISA v3.0b Figure 35 on Radix. Based on x86 implementation: commit4fc19708b1("x86/alternatives: Initialize temporary mm for patching") and: commitb3fd8e83ad("x86/alternatives: Use temporary mm for text poking") From: Benjamin Gray <bgray@linux.ibm.com> Synchronisation is done according to ISA 3.1B Book 3 Chapter 13 "Synchronization Requirements for Context Alterations". Switching the mm is a change to the PID, which requires a CSI before and after the change, and a hwsync between the last instruction that performs address translation for an associated storage access. Instruction fetch is an associated storage access, but the instruction address mappings are not being changed, so it should not matter which context they use. We must still perform a hwsync to guard arbitrary prior code that may have accessed a userspace address. TLB invalidation is local and VA specific. Local because only this core used the patching mm, and VA specific because we only care that the writable mapping is purged. Leaving the other mappings intact is more efficient, especially when performing many code patches in a row (e.g., as ftrace would). Signed-off-by: Christopher M. Riedl <cmr@bluescreens.de> Signed-off-by: Benjamin Gray <bgray@linux.ibm.com> [mpe: Use mm_alloc() per 107b6828a7cd ("x86/mm: Use mm_alloc() in poking_init()")] Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20221109045112.187069-9-bgray@linux.ibm.com
This commit is contained in:
Christopher M. Riedl
Michael Ellerman
Родитель
274d842fa1
Коммит
c28c15b6d2
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@ -4,12 +4,17 @@
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*/
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#include <linux/kprobes.h>
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#include <linux/mmu_context.h>
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#include <linux/random.h>
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#include <linux/vmalloc.h>
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#include <linux/init.h>
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#include <linux/cpuhotplug.h>
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#include <linux/uaccess.h>
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#include <linux/jump_label.h>
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#include <asm/debug.h>
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#include <asm/pgalloc.h>
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#include <asm/tlb.h>
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#include <asm/tlbflush.h>
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#include <asm/page.h>
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#include <asm/code-patching.h>
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@ -42,11 +47,54 @@ int raw_patch_instruction(u32 *addr, ppc_inst_t instr)
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}
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#ifdef CONFIG_STRICT_KERNEL_RWX
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static DEFINE_PER_CPU(struct vm_struct *, text_poke_area);
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static DEFINE_PER_CPU(struct mm_struct *, cpu_patching_mm);
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static DEFINE_PER_CPU(unsigned long, cpu_patching_addr);
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static DEFINE_PER_CPU(pte_t *, cpu_patching_pte);
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static int map_patch_area(void *addr, unsigned long text_poke_addr);
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static void unmap_patch_area(unsigned long addr);
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static bool mm_patch_enabled(void)
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{
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return IS_ENABLED(CONFIG_SMP) && radix_enabled();
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}
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/*
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* The following applies for Radix MMU. Hash MMU has different requirements,
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* and so is not supported.
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*
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* Changing mm requires context synchronising instructions on both sides of
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* the context switch, as well as a hwsync between the last instruction for
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* which the address of an associated storage access was translated using
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* the current context.
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*
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* switch_mm_irqs_off() performs an isync after the context switch. It is
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* the responsibility of the caller to perform the CSI and hwsync before
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* starting/stopping the temp mm.
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*/
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static struct mm_struct *start_using_temp_mm(struct mm_struct *temp_mm)
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{
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struct mm_struct *orig_mm = current->active_mm;
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lockdep_assert_irqs_disabled();
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switch_mm_irqs_off(orig_mm, temp_mm, current);
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WARN_ON(!mm_is_thread_local(temp_mm));
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suspend_breakpoints();
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return orig_mm;
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}
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static void stop_using_temp_mm(struct mm_struct *temp_mm,
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struct mm_struct *orig_mm)
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{
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lockdep_assert_irqs_disabled();
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switch_mm_irqs_off(temp_mm, orig_mm, current);
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restore_breakpoints();
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}
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static int text_area_cpu_up(unsigned int cpu)
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{
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struct vm_struct *area;
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@ -79,14 +127,86 @@ static int text_area_cpu_down(unsigned int cpu)
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return 0;
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}
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static void put_patching_mm(struct mm_struct *mm, unsigned long patching_addr)
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{
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struct mmu_gather tlb;
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tlb_gather_mmu(&tlb, mm);
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free_pgd_range(&tlb, patching_addr, patching_addr + PAGE_SIZE, 0, 0);
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mmput(mm);
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}
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static int text_area_cpu_up_mm(unsigned int cpu)
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{
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struct mm_struct *mm;
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unsigned long addr;
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pte_t *pte;
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spinlock_t *ptl;
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mm = mm_alloc();
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if (WARN_ON(!mm))
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goto fail_no_mm;
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/*
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* Choose a random page-aligned address from the interval
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* [PAGE_SIZE .. DEFAULT_MAP_WINDOW - PAGE_SIZE].
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* The lower address bound is PAGE_SIZE to avoid the zero-page.
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*/
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addr = (1 + (get_random_long() % (DEFAULT_MAP_WINDOW / PAGE_SIZE - 2))) << PAGE_SHIFT;
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/*
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* PTE allocation uses GFP_KERNEL which means we need to
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* pre-allocate the PTE here because we cannot do the
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* allocation during patching when IRQs are disabled.
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*
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* Using get_locked_pte() to avoid open coding, the lock
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* is unnecessary.
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*/
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pte = get_locked_pte(mm, addr, &ptl);
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if (!pte)
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goto fail_no_pte;
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pte_unmap_unlock(pte, ptl);
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this_cpu_write(cpu_patching_mm, mm);
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this_cpu_write(cpu_patching_addr, addr);
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this_cpu_write(cpu_patching_pte, pte);
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return 0;
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fail_no_pte:
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put_patching_mm(mm, addr);
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fail_no_mm:
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return -ENOMEM;
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}
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static int text_area_cpu_down_mm(unsigned int cpu)
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{
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put_patching_mm(this_cpu_read(cpu_patching_mm),
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this_cpu_read(cpu_patching_addr));
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this_cpu_write(cpu_patching_mm, NULL);
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this_cpu_write(cpu_patching_addr, 0);
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this_cpu_write(cpu_patching_pte, NULL);
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return 0;
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}
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static __ro_after_init DEFINE_STATIC_KEY_FALSE(poking_init_done);
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void __init poking_init(void)
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{
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int ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
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"powerpc/text_poke:online",
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text_area_cpu_up,
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text_area_cpu_down);
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int ret;
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if (mm_patch_enabled())
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ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
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"powerpc/text_poke_mm:online",
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text_area_cpu_up_mm,
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text_area_cpu_down_mm);
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else
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ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
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"powerpc/text_poke:online",
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text_area_cpu_up,
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text_area_cpu_down);
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/* cpuhp_setup_state returns >= 0 on success */
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if (WARN_ON(ret < 0))
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@ -148,6 +268,50 @@ static void unmap_patch_area(unsigned long addr)
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flush_tlb_kernel_range(addr, addr + PAGE_SIZE);
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}
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static int __do_patch_instruction_mm(u32 *addr, ppc_inst_t instr)
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{
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int err;
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u32 *patch_addr;
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unsigned long text_poke_addr;
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pte_t *pte;
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unsigned long pfn = get_patch_pfn(addr);
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struct mm_struct *patching_mm;
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struct mm_struct *orig_mm;
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patching_mm = __this_cpu_read(cpu_patching_mm);
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pte = __this_cpu_read(cpu_patching_pte);
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text_poke_addr = __this_cpu_read(cpu_patching_addr);
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patch_addr = (u32 *)(text_poke_addr + offset_in_page(addr));
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__set_pte_at(patching_mm, text_poke_addr, pte, pfn_pte(pfn, PAGE_KERNEL), 0);
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/* order PTE update before use, also serves as the hwsync */
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asm volatile("ptesync": : :"memory");
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/* order context switch after arbitrary prior code */
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isync();
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orig_mm = start_using_temp_mm(patching_mm);
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err = __patch_instruction(addr, instr, patch_addr);
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/* hwsync performed by __patch_instruction (sync) if successful */
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if (err)
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mb(); /* sync */
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/* context synchronisation performed by __patch_instruction (isync or exception) */
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stop_using_temp_mm(patching_mm, orig_mm);
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pte_clear(patching_mm, text_poke_addr, pte);
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/*
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* ptesync to order PTE update before TLB invalidation done
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* by radix__local_flush_tlb_page_psize (in _tlbiel_va)
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*/
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local_flush_tlb_page_psize(patching_mm, text_poke_addr, mmu_virtual_psize);
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return err;
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}
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static int __do_patch_instruction(u32 *addr, ppc_inst_t instr)
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{
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int err;
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@ -187,7 +351,10 @@ static int do_patch_instruction(u32 *addr, ppc_inst_t instr)
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return raw_patch_instruction(addr, instr);
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local_irq_save(flags);
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err = __do_patch_instruction(addr, instr);
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if (mm_patch_enabled())
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err = __do_patch_instruction_mm(addr, instr);
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else
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err = __do_patch_instruction(addr, instr);
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local_irq_restore(flags);
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return err;
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