[PATCH] x86_64: Support constantly ticking TSCs
On Intel Noconas the TSC ticks with a constant frequency. Don't scale the factor used by udelay when cpufreq changes the frequency. This generalizes an earlier patch by Intel for this. Cc: <venkatesh.pallipadi@intel.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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dc37db4d8c
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c29601e9c1
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@ -855,6 +855,8 @@ static void __init init_intel(struct cpuinfo_x86 *c)
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if (c->x86 == 15)
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if (c->x86 == 15)
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c->x86_cache_alignment = c->x86_clflush_size * 2;
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c->x86_cache_alignment = c->x86_clflush_size * 2;
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if (c->x86 >= 15)
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set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
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}
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}
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void __init get_cpu_vendor(struct cpuinfo_x86 *c)
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void __init get_cpu_vendor(struct cpuinfo_x86 *c)
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@ -1055,7 +1057,8 @@ static int show_cpuinfo(struct seq_file *m, void *v)
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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/* Other (Linux-defined) */
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/* Other (Linux-defined) */
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"cxmmx", "k6_mtrr", "cyrix_arr", "centaur_mcr", NULL, NULL, NULL, NULL,
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"cxmmx", NULL, "cyrix_arr", "centaur_mcr", "k8c+",
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"constant_tsc", NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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@ -614,6 +614,9 @@ static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
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struct cpufreq_freqs *freq = data;
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struct cpufreq_freqs *freq = data;
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unsigned long *lpj, dummy;
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unsigned long *lpj, dummy;
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if (cpu_has(&cpu_data[freq->cpu], X86_FEATURE_CONSTANT_TSC))
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return 0;
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lpj = &dummy;
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lpj = &dummy;
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if (!(freq->flags & CPUFREQ_CONST_LOOPS))
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if (!(freq->flags & CPUFREQ_CONST_LOOPS))
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#ifdef CONFIG_SMP
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#ifdef CONFIG_SMP
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@ -622,8 +625,6 @@ static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
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lpj = &boot_cpu_data.loops_per_jiffy;
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lpj = &boot_cpu_data.loops_per_jiffy;
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#endif
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#endif
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if (!ref_freq) {
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if (!ref_freq) {
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ref_freq = freq->old;
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ref_freq = freq->old;
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loops_per_jiffy_ref = *lpj;
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loops_per_jiffy_ref = *lpj;
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@ -62,6 +62,7 @@
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#define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */
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#define X86_FEATURE_CYRIX_ARR (3*32+ 2) /* Cyrix ARRs (= MTRRs) */
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#define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */
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#define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */
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#define X86_FEATURE_K8_C (3*32+ 4) /* C stepping K8 */
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#define X86_FEATURE_K8_C (3*32+ 4) /* C stepping K8 */
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#define X86_FEATURE_CONSTANT_TSC (3*32+5) /* TSC runs at constant rate */
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/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
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/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
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#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
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#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
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