[media] coda: dynamic IRAM setup for encoder
This sets up IRAM areas used as temporary memory for the different hardware units depending on the frame size. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Kamil Debski <k.debski@samsung.com> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
This commit is contained in:
Philipp Zabel
Mauro Carvalho Chehab
Родитель
366108f0ec
Коммит
c2d2251ac9
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@ -160,6 +160,18 @@ struct coda_params {
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u32 slice_max_mb;
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};
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struct coda_iram_info {
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u32 axi_sram_use;
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phys_addr_t buf_bit_use;
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phys_addr_t buf_ip_ac_dc_use;
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phys_addr_t buf_dbk_y_use;
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phys_addr_t buf_dbk_c_use;
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phys_addr_t buf_ovl_use;
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phys_addr_t buf_btp_use;
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phys_addr_t search_ram_paddr;
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int search_ram_size;
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};
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struct coda_ctx {
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struct coda_dev *dev;
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struct list_head list;
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@ -182,6 +194,7 @@ struct coda_ctx {
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struct coda_aux_buf internal_frames[CODA_MAX_FRAMEBUFFERS];
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int num_internal_frames;
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int idx;
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struct coda_iram_info iram_info;
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};
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static const u8 coda_filler_nal[14] = { 0x00, 0x00, 0x00, 0x01, 0x0c, 0xff,
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@ -800,6 +813,10 @@ static void coda_device_run(void *m2m_priv)
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CODA7_REG_BIT_AXI_SRAM_USE);
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}
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if (dev->devtype->product != CODA_DX6)
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coda_write(dev, ctx->iram_info.axi_sram_use,
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CODA7_REG_BIT_AXI_SRAM_USE);
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/* 1 second timeout in case CODA locks up */
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schedule_delayed_work(&dev->timeout, HZ);
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@ -1035,6 +1052,110 @@ static int coda_h264_padding(int size, char *p)
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return nal_size;
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}
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static void coda_setup_iram(struct coda_ctx *ctx)
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{
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struct coda_iram_info *iram_info = &ctx->iram_info;
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struct coda_dev *dev = ctx->dev;
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int ipacdc_size;
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int bitram_size;
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int dbk_size;
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int mb_width;
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int me_size;
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int size;
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memset(iram_info, 0, sizeof(*iram_info));
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size = dev->iram_size;
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if (dev->devtype->product == CODA_DX6)
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return;
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if (ctx->inst_type == CODA_INST_ENCODER) {
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struct coda_q_data *q_data_src;
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q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
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mb_width = DIV_ROUND_UP(q_data_src->width, 16);
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/* Prioritize in case IRAM is too small for everything */
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me_size = round_up(round_up(q_data_src->width, 16) * 36 + 2048,
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1024);
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iram_info->search_ram_size = me_size;
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if (size >= iram_info->search_ram_size) {
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if (dev->devtype->product == CODA_7541)
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iram_info->axi_sram_use |= CODA7_USE_HOST_ME_ENABLE;
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iram_info->search_ram_paddr = dev->iram_paddr;
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size -= iram_info->search_ram_size;
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} else {
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pr_err("IRAM is smaller than the search ram size\n");
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goto out;
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}
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/* Only H.264BP and H.263P3 are considered */
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dbk_size = round_up(128 * mb_width, 1024);
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if (size >= dbk_size) {
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iram_info->axi_sram_use |= CODA7_USE_HOST_DBK_ENABLE;
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iram_info->buf_dbk_y_use = dev->iram_paddr +
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iram_info->search_ram_size;
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iram_info->buf_dbk_c_use = iram_info->buf_dbk_y_use +
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dbk_size / 2;
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size -= dbk_size;
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} else {
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goto out;
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}
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bitram_size = round_up(128 * mb_width, 1024);
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if (size >= bitram_size) {
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iram_info->axi_sram_use |= CODA7_USE_HOST_BIT_ENABLE;
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iram_info->buf_bit_use = iram_info->buf_dbk_c_use +
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dbk_size / 2;
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size -= bitram_size;
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} else {
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goto out;
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}
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ipacdc_size = round_up(128 * mb_width, 1024);
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if (size >= ipacdc_size) {
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iram_info->axi_sram_use |= CODA7_USE_HOST_IP_ENABLE;
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iram_info->buf_ip_ac_dc_use = iram_info->buf_bit_use +
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bitram_size;
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size -= ipacdc_size;
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}
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/* OVL disabled for encoder */
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}
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out:
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switch (dev->devtype->product) {
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case CODA_DX6:
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break;
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case CODA_7541:
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/* i.MX53 uses secondary AXI for IRAM access */
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if (iram_info->axi_sram_use & CODA7_USE_HOST_BIT_ENABLE)
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iram_info->axi_sram_use |= CODA7_USE_BIT_ENABLE;
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if (iram_info->axi_sram_use & CODA7_USE_HOST_IP_ENABLE)
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iram_info->axi_sram_use |= CODA7_USE_IP_ENABLE;
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if (iram_info->axi_sram_use & CODA7_USE_HOST_DBK_ENABLE)
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iram_info->axi_sram_use |= CODA7_USE_DBK_ENABLE;
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if (iram_info->axi_sram_use & CODA7_USE_HOST_OVL_ENABLE)
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iram_info->axi_sram_use |= CODA7_USE_OVL_ENABLE;
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if (iram_info->axi_sram_use & CODA7_USE_HOST_ME_ENABLE)
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iram_info->axi_sram_use |= CODA7_USE_ME_ENABLE;
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}
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if (!(iram_info->axi_sram_use & CODA7_USE_HOST_IP_ENABLE))
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v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
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"IRAM smaller than needed\n");
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if (dev->devtype->product == CODA_7541) {
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/* TODO - Enabling these causes picture errors on CODA7541 */
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if (ctx->inst_type == CODA_INST_ENCODER) {
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iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
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CODA7_USE_HOST_DBK_ENABLE |
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CODA7_USE_IP_ENABLE |
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CODA7_USE_DBK_ENABLE);
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}
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}
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}
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static int coda_encode_header(struct coda_ctx *ctx, struct vb2_buffer *buf,
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int header_code, u8 *header, int *size)
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{
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@ -1207,6 +1328,8 @@ static int coda_start_streaming(struct vb2_queue *q, unsigned int count)
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}
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coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
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coda_setup_iram(ctx);
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if (dst_fourcc == V4L2_PIX_FMT_H264) {
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value = (FMO_SLICE_SAVE_BUF_SIZE << 7);
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value |= (0 & CODA_FMOPARAM_TYPE_MASK) << CODA_FMOPARAM_TYPE_OFFSET;
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@ -1214,8 +1337,10 @@ static int coda_start_streaming(struct vb2_queue *q, unsigned int count)
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if (dev->devtype->product == CODA_DX6) {
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coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
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} else {
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coda_write(dev, dev->iram_paddr, CODA7_CMD_ENC_SEQ_SEARCH_BASE);
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coda_write(dev, 48 * 1024, CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
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coda_write(dev, ctx->iram_info.search_ram_paddr,
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CODA7_CMD_ENC_SEQ_SEARCH_BASE);
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coda_write(dev, ctx->iram_info.search_ram_size,
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CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
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}
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}
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@ -1240,12 +1365,16 @@ static int coda_start_streaming(struct vb2_queue *q, unsigned int count)
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coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
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coda_write(dev, round_up(q_data_src->width, 8), CODA_CMD_SET_FRAME_BUF_STRIDE);
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if (dev->devtype->product != CODA_DX6) {
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coda_write(dev, round_up(q_data_src->width, 8), CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
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coda_write(dev, dev->iram_paddr + 48 * 1024, CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
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coda_write(dev, dev->iram_paddr + 53 * 1024, CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
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coda_write(dev, dev->iram_paddr + 58 * 1024, CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
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coda_write(dev, dev->iram_paddr + 68 * 1024, CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
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coda_write(dev, 0x0, CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
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coda_write(dev, ctx->iram_info.buf_bit_use,
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CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
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coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
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CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
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coda_write(dev, ctx->iram_info.buf_dbk_y_use,
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CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
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coda_write(dev, ctx->iram_info.buf_dbk_c_use,
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CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
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coda_write(dev, ctx->iram_info.buf_ovl_use,
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CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
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}
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ret = coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF);
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if (ret < 0) {
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@ -47,10 +47,17 @@
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#define CODA_REG_BIT_WR_PTR(x) (0x124 + 8 * (x))
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#define CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR 0x140
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#define CODA7_REG_BIT_AXI_SRAM_USE 0x140
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#define CODA7_USE_BIT_ENABLE (1 << 0)
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#define CODA7_USE_HOST_ME_ENABLE (1 << 11)
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#define CODA7_USE_HOST_OVL_ENABLE (1 << 10)
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#define CODA7_USE_HOST_DBK_ENABLE (1 << 9)
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#define CODA7_USE_HOST_IP_ENABLE (1 << 8)
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#define CODA7_USE_HOST_BIT_ENABLE (1 << 7)
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#define CODA7_USE_ME_ENABLE (1 << 4)
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#define CODA7_USE_HOST_ME_ENABLE (1 << 11)
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#define CODA7_USE_OVL_ENABLE (1 << 3)
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#define CODA7_USE_DBK_ENABLE (1 << 2)
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#define CODA7_USE_IP_ENABLE (1 << 1)
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#define CODA7_USE_BIT_ENABLE (1 << 0)
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#define CODA_REG_BIT_BUSY 0x160
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#define CODA_REG_BIT_BUSY_FLAG 1
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#define CODA_REG_BIT_RUN_COMMAND 0x164
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