dmaengine: stm32-dma: fix DMA IRQ status handling
Update the way Transfer Complete and Half Transfer Complete status are acknowledge. Even if HTI is not enabled its status is shown when reading registers, driver has to clear it gently and not raise an error. Signed-off-by: Pierre-Yves MORDRET <pierre-yves.mordret@st.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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a2b6103b7a
Коммит
c2d86b1cd6
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@ -34,9 +34,14 @@
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#define STM32_DMA_LIFCR 0x0008 /* DMA Low Int Flag Clear Reg */
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#define STM32_DMA_HIFCR 0x000c /* DMA High Int Flag Clear Reg */
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#define STM32_DMA_TCI BIT(5) /* Transfer Complete Interrupt */
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#define STM32_DMA_HTI BIT(4) /* Half Transfer Interrupt */
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#define STM32_DMA_TEI BIT(3) /* Transfer Error Interrupt */
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#define STM32_DMA_DMEI BIT(2) /* Direct Mode Error Interrupt */
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#define STM32_DMA_FEI BIT(0) /* FIFO Error Interrupt */
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#define STM32_DMA_MASKI (STM32_DMA_TCI \
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| STM32_DMA_TEI \
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| STM32_DMA_DMEI \
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| STM32_DMA_FEI)
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/* DMA Stream x Configuration Register */
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#define STM32_DMA_SCR(x) (0x0010 + 0x18 * (x)) /* x = 0..7 */
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@ -643,13 +648,29 @@ static irqreturn_t stm32_dma_chan_irq(int irq, void *devid)
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status = stm32_dma_irq_status(chan);
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scr = stm32_dma_read(dmadev, STM32_DMA_SCR(chan->id));
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if ((status & STM32_DMA_TCI) && (scr & STM32_DMA_SCR_TCIE)) {
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if (status & STM32_DMA_TCI) {
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stm32_dma_irq_clear(chan, STM32_DMA_TCI);
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stm32_dma_handle_chan_done(chan);
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} else {
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if (scr & STM32_DMA_SCR_TCIE)
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stm32_dma_handle_chan_done(chan);
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status &= ~STM32_DMA_TCI;
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}
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if (status & STM32_DMA_HTI) {
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stm32_dma_irq_clear(chan, STM32_DMA_HTI);
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status &= ~STM32_DMA_HTI;
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}
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if (status & STM32_DMA_FEI) {
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stm32_dma_irq_clear(chan, STM32_DMA_FEI);
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status &= ~STM32_DMA_FEI;
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if (!(scr & STM32_DMA_SCR_EN))
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dev_err(chan2dev(chan), "FIFO Error\n");
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else
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dev_dbg(chan2dev(chan), "FIFO over/underrun\n");
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}
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if (status) {
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stm32_dma_irq_clear(chan, status);
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dev_err(chan2dev(chan), "DMA error: status=0x%08x\n", status);
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if (!(scr & STM32_DMA_SCR_EN))
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dev_err(chan2dev(chan), "chan disabled by HW\n");
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}
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spin_unlock(&chan->vchan.lock);
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