powerpc/powernv: display reason for Malfunction Alert HMI.
The V2 version of HMI event now carries additional information for Malfunction Alert. It now contains error information about CORE and NX checkstop. This patch checks and displays the check stop reason before panic. Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> Acked-by: Stewart Smith <stewart@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Mahesh Salgaonkar
Michael Ellerman
Родитель
5d83c2b37d
Коммит
c33e11d0dd
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@ -437,6 +437,7 @@ struct OpalMemoryErrorData {
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/* HMI interrupt event */
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enum OpalHMI_Version {
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OpalHMIEvt_V1 = 1,
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OpalHMIEvt_V2 = 2,
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};
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enum OpalHMI_Severity {
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@ -467,6 +468,49 @@ enum OpalHMI_ErrType {
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OpalHMI_ERROR_CAPP_RECOVERY,
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};
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enum OpalHMI_XstopType {
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CHECKSTOP_TYPE_UNKNOWN = 0,
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CHECKSTOP_TYPE_CORE = 1,
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CHECKSTOP_TYPE_NX = 2,
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};
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enum OpalHMI_CoreXstopReason {
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CORE_CHECKSTOP_IFU_REGFILE = 0x00000001,
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CORE_CHECKSTOP_IFU_LOGIC = 0x00000002,
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CORE_CHECKSTOP_PC_DURING_RECOV = 0x00000004,
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CORE_CHECKSTOP_ISU_REGFILE = 0x00000008,
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CORE_CHECKSTOP_ISU_LOGIC = 0x00000010,
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CORE_CHECKSTOP_FXU_LOGIC = 0x00000020,
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CORE_CHECKSTOP_VSU_LOGIC = 0x00000040,
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CORE_CHECKSTOP_PC_RECOV_IN_MAINT_MODE = 0x00000080,
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CORE_CHECKSTOP_LSU_REGFILE = 0x00000100,
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CORE_CHECKSTOP_PC_FWD_PROGRESS = 0x00000200,
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CORE_CHECKSTOP_LSU_LOGIC = 0x00000400,
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CORE_CHECKSTOP_PC_LOGIC = 0x00000800,
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CORE_CHECKSTOP_PC_HYP_RESOURCE = 0x00001000,
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CORE_CHECKSTOP_PC_HANG_RECOV_FAILED = 0x00002000,
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CORE_CHECKSTOP_PC_AMBI_HANG_DETECTED = 0x00004000,
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CORE_CHECKSTOP_PC_DEBUG_TRIG_ERR_INJ = 0x00008000,
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CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ = 0x00010000,
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};
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enum OpalHMI_NestAccelXstopReason {
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NX_CHECKSTOP_SHM_INVAL_STATE_ERR = 0x00000001,
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NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1 = 0x00000002,
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NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2 = 0x00000004,
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NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR = 0x00000008,
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NX_CHECKSTOP_DMA_CH1_INVAL_STATE_ERR = 0x00000010,
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NX_CHECKSTOP_DMA_CH2_INVAL_STATE_ERR = 0x00000020,
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NX_CHECKSTOP_DMA_CH3_INVAL_STATE_ERR = 0x00000040,
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NX_CHECKSTOP_DMA_CH4_INVAL_STATE_ERR = 0x00000080,
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NX_CHECKSTOP_DMA_CH5_INVAL_STATE_ERR = 0x00000100,
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NX_CHECKSTOP_DMA_CH6_INVAL_STATE_ERR = 0x00000200,
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NX_CHECKSTOP_DMA_CH7_INVAL_STATE_ERR = 0x00000400,
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NX_CHECKSTOP_DMA_CRB_UE = 0x00000800,
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NX_CHECKSTOP_DMA_CRB_SUE = 0x00001000,
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NX_CHECKSTOP_PBI_ISN_UE = 0x00002000,
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};
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struct OpalHMIEvent {
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uint8_t version; /* 0x00 */
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uint8_t severity; /* 0x01 */
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@ -477,6 +521,23 @@ struct OpalHMIEvent {
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__be64 hmer;
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/* TFMR register. Valid only for TFAC and TFMR_PARITY error type. */
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__be64 tfmr;
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/* version 2 and later */
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union {
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/*
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* checkstop info (Core/NX).
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* Valid for OpalHMI_ERROR_MALFUNC_ALERT.
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*/
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struct {
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uint8_t xstop_type; /* enum OpalHMI_XstopType */
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uint8_t reserved_1[3];
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__be32 xstop_reason;
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union {
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__be32 pir; /* for CHECKSTOP_TYPE_CORE */
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__be32 chip_id; /* for CHECKSTOP_TYPE_NX */
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} u;
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} xstop_error;
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} u;
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};
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enum {
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@ -35,9 +35,134 @@ struct OpalHmiEvtNode {
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struct list_head list;
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struct OpalHMIEvent hmi_evt;
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};
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struct xstop_reason {
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uint32_t xstop_reason;
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const char *unit_failed;
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const char *description;
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};
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static LIST_HEAD(opal_hmi_evt_list);
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static DEFINE_SPINLOCK(opal_hmi_evt_lock);
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static void print_core_checkstop_reason(const char *level,
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struct OpalHMIEvent *hmi_evt)
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{
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int i;
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static const struct xstop_reason xstop_reason[] = {
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{ CORE_CHECKSTOP_IFU_REGFILE, "IFU",
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"RegFile core check stop" },
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{ CORE_CHECKSTOP_IFU_LOGIC, "IFU", "Logic core check stop" },
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{ CORE_CHECKSTOP_PC_DURING_RECOV, "PC",
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"Core checkstop during recovery" },
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{ CORE_CHECKSTOP_ISU_REGFILE, "ISU",
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"RegFile core check stop (mapper error)" },
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{ CORE_CHECKSTOP_ISU_LOGIC, "ISU", "Logic core check stop" },
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{ CORE_CHECKSTOP_FXU_LOGIC, "FXU", "Logic core check stop" },
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{ CORE_CHECKSTOP_VSU_LOGIC, "VSU", "Logic core check stop" },
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{ CORE_CHECKSTOP_PC_RECOV_IN_MAINT_MODE, "PC",
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"Recovery in maintenance mode" },
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{ CORE_CHECKSTOP_LSU_REGFILE, "LSU",
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"RegFile core check stop" },
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{ CORE_CHECKSTOP_PC_FWD_PROGRESS, "PC",
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"Forward Progress Error" },
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{ CORE_CHECKSTOP_LSU_LOGIC, "LSU", "Logic core check stop" },
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{ CORE_CHECKSTOP_PC_LOGIC, "PC", "Logic core check stop" },
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{ CORE_CHECKSTOP_PC_HYP_RESOURCE, "PC",
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"Hypervisor Resource error - core check stop" },
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{ CORE_CHECKSTOP_PC_HANG_RECOV_FAILED, "PC",
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"Hang Recovery Failed (core check stop)" },
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{ CORE_CHECKSTOP_PC_AMBI_HANG_DETECTED, "PC",
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"Ambiguous Hang Detected (unknown source)" },
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{ CORE_CHECKSTOP_PC_DEBUG_TRIG_ERR_INJ, "PC",
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"Debug Trigger Error inject" },
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{ CORE_CHECKSTOP_PC_SPRD_HYP_ERR_INJ, "PC",
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"Hypervisor check stop via SPRC/SPRD" },
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};
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/* Validity check */
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if (!hmi_evt->u.xstop_error.xstop_reason) {
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printk("%s Unknown Core check stop.\n", level);
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return;
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}
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printk("%s CPU PIR: %08x\n", level,
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be32_to_cpu(hmi_evt->u.xstop_error.u.pir));
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for (i = 0; i < ARRAY_SIZE(xstop_reason); i++)
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if (be32_to_cpu(hmi_evt->u.xstop_error.xstop_reason) &
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xstop_reason[i].xstop_reason)
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printk("%s [Unit: %-3s] %s\n", level,
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xstop_reason[i].unit_failed,
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xstop_reason[i].description);
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}
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static void print_nx_checkstop_reason(const char *level,
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struct OpalHMIEvent *hmi_evt)
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{
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int i;
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static const struct xstop_reason xstop_reason[] = {
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{ NX_CHECKSTOP_SHM_INVAL_STATE_ERR, "DMA & Engine",
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"SHM invalid state error" },
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{ NX_CHECKSTOP_DMA_INVAL_STATE_ERR_1, "DMA & Engine",
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"DMA invalid state error bit 15" },
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{ NX_CHECKSTOP_DMA_INVAL_STATE_ERR_2, "DMA & Engine",
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"DMA invalid state error bit 16" },
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{ NX_CHECKSTOP_DMA_CH0_INVAL_STATE_ERR, "DMA & Engine",
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"Channel 0 invalid state error" },
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{ NX_CHECKSTOP_DMA_CH1_INVAL_STATE_ERR, "DMA & Engine",
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"Channel 1 invalid state error" },
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{ NX_CHECKSTOP_DMA_CH2_INVAL_STATE_ERR, "DMA & Engine",
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"Channel 2 invalid state error" },
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{ NX_CHECKSTOP_DMA_CH3_INVAL_STATE_ERR, "DMA & Engine",
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"Channel 3 invalid state error" },
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{ NX_CHECKSTOP_DMA_CH4_INVAL_STATE_ERR, "DMA & Engine",
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"Channel 4 invalid state error" },
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{ NX_CHECKSTOP_DMA_CH5_INVAL_STATE_ERR, "DMA & Engine",
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"Channel 5 invalid state error" },
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{ NX_CHECKSTOP_DMA_CH6_INVAL_STATE_ERR, "DMA & Engine",
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"Channel 6 invalid state error" },
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{ NX_CHECKSTOP_DMA_CH7_INVAL_STATE_ERR, "DMA & Engine",
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"Channel 7 invalid state error" },
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{ NX_CHECKSTOP_DMA_CRB_UE, "DMA & Engine",
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"UE error on CRB(CSB address, CCB)" },
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{ NX_CHECKSTOP_DMA_CRB_SUE, "DMA & Engine",
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"SUE error on CRB(CSB address, CCB)" },
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{ NX_CHECKSTOP_PBI_ISN_UE, "PowerBus Interface",
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"CRB Kill ISN received while holding ISN with UE error" },
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};
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/* Validity check */
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if (!hmi_evt->u.xstop_error.xstop_reason) {
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printk("%s Unknown NX check stop.\n", level);
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return;
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}
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printk("%s NX checkstop on CHIP ID: %x\n", level,
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be32_to_cpu(hmi_evt->u.xstop_error.u.chip_id));
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for (i = 0; i < ARRAY_SIZE(xstop_reason); i++)
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if (be32_to_cpu(hmi_evt->u.xstop_error.xstop_reason) &
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xstop_reason[i].xstop_reason)
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printk("%s [Unit: %-3s] %s\n", level,
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xstop_reason[i].unit_failed,
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xstop_reason[i].description);
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}
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static void print_checkstop_reason(const char *level,
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struct OpalHMIEvent *hmi_evt)
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{
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switch (hmi_evt->u.xstop_error.xstop_type) {
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case CHECKSTOP_TYPE_CORE:
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print_core_checkstop_reason(level, hmi_evt);
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break;
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case CHECKSTOP_TYPE_NX:
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print_nx_checkstop_reason(level, hmi_evt);
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break;
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case CHECKSTOP_TYPE_UNKNOWN:
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printk("%s Unknown Malfunction Alert.\n", level);
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break;
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}
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}
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static void print_hmi_event_info(struct OpalHMIEvent *hmi_evt)
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{
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const char *level, *sevstr, *error_info;
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@ -95,6 +220,13 @@ static void print_hmi_event_info(struct OpalHMIEvent *hmi_evt)
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(hmi_evt->type == OpalHMI_ERROR_TFMR_PARITY))
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printk("%s TFMR: %016llx\n", level,
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be64_to_cpu(hmi_evt->tfmr));
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if (hmi_evt->version < OpalHMIEvt_V2)
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return;
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/* OpalHMIEvt_V2 and above provides reason for malfunction alert. */
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if (hmi_evt->type == OpalHMI_ERROR_MALFUNC_ALERT)
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print_checkstop_reason(level, hmi_evt);
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}
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static void hmi_event_handler(struct work_struct *work)
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