net/mlx5: DR, Add STEv1 modify header logic
Add HW specific modify header fields and logic to STEv1 file. Since STEv0 and STEv1 modify actions values are different, each version has its own implementation. Signed-off-by: Alex Vesker <valex@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
This commit is contained in:
Yevgeny Kliteynik
Saeed Mahameed
Родитель
4e856c5db9
Коммит
c349b4137c
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@ -95,6 +95,159 @@ enum dr_ste_v1_action_id {
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DR_STE_V1_ACTION_ID_SPECIAL_ENCAP_L3 = 0x22,
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};
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enum {
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DR_STE_V1_ACTION_MDFY_FLD_L2_OUT_0 = 0x00,
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DR_STE_V1_ACTION_MDFY_FLD_L2_OUT_1 = 0x01,
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DR_STE_V1_ACTION_MDFY_FLD_L2_OUT_2 = 0x02,
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DR_STE_V1_ACTION_MDFY_FLD_SRC_L2_OUT_0 = 0x08,
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DR_STE_V1_ACTION_MDFY_FLD_SRC_L2_OUT_1 = 0x09,
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DR_STE_V1_ACTION_MDFY_FLD_L3_OUT_0 = 0x0e,
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DR_STE_V1_ACTION_MDFY_FLD_L4_OUT_0 = 0x18,
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DR_STE_V1_ACTION_MDFY_FLD_L4_OUT_1 = 0x19,
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DR_STE_V1_ACTION_MDFY_FLD_IPV4_OUT_0 = 0x40,
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DR_STE_V1_ACTION_MDFY_FLD_IPV4_OUT_1 = 0x41,
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DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_0 = 0x44,
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DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_1 = 0x45,
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DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_2 = 0x46,
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DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_3 = 0x47,
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DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_0 = 0x4c,
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DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_1 = 0x4d,
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DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_2 = 0x4e,
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DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_3 = 0x4f,
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DR_STE_V1_ACTION_MDFY_FLD_TCP_MISC_0 = 0x5e,
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DR_STE_V1_ACTION_MDFY_FLD_TCP_MISC_1 = 0x5f,
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DR_STE_V1_ACTION_MDFY_FLD_METADATA_2_CQE = 0x7b,
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DR_STE_V1_ACTION_MDFY_FLD_GNRL_PURPOSE = 0x7c,
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DR_STE_V1_ACTION_MDFY_FLD_REGISTER_2 = 0x8c,
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DR_STE_V1_ACTION_MDFY_FLD_REGISTER_3 = 0x8d,
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DR_STE_V1_ACTION_MDFY_FLD_REGISTER_4 = 0x8e,
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DR_STE_V1_ACTION_MDFY_FLD_REGISTER_5 = 0x8f,
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DR_STE_V1_ACTION_MDFY_FLD_REGISTER_6 = 0x90,
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DR_STE_V1_ACTION_MDFY_FLD_REGISTER_7 = 0x91,
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};
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static const struct mlx5dr_ste_action_modify_field dr_ste_v1_action_modify_field_arr[] = {
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[MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_SRC_L2_OUT_0, .start = 0, .end = 31,
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},
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[MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_SRC_L2_OUT_1, .start = 16, .end = 31,
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},
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[MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_L2_OUT_1, .start = 0, .end = 15,
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},
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[MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_L2_OUT_0, .start = 0, .end = 31,
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},
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[MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_L2_OUT_1, .start = 16, .end = 31,
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},
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[MLX5_ACTION_IN_FIELD_OUT_IP_DSCP] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_L3_OUT_0, .start = 18, .end = 23,
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},
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[MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_L4_OUT_1, .start = 16, .end = 24,
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.l4_type = DR_STE_ACTION_MDFY_TYPE_L4_TCP,
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},
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[MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_L4_OUT_0, .start = 16, .end = 31,
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.l4_type = DR_STE_ACTION_MDFY_TYPE_L4_TCP,
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},
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[MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_L4_OUT_0, .start = 0, .end = 15,
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.l4_type = DR_STE_ACTION_MDFY_TYPE_L4_TCP,
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},
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[MLX5_ACTION_IN_FIELD_OUT_IP_TTL] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_L3_OUT_0, .start = 8, .end = 15,
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.l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV4,
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},
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[MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_L3_OUT_0, .start = 8, .end = 15,
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.l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
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},
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[MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_L4_OUT_0, .start = 16, .end = 31,
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.l4_type = DR_STE_ACTION_MDFY_TYPE_L4_UDP,
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},
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[MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_L4_OUT_0, .start = 0, .end = 15,
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.l4_type = DR_STE_ACTION_MDFY_TYPE_L4_UDP,
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},
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[MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_0, .start = 0, .end = 31,
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.l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
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},
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[MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_1, .start = 0, .end = 31,
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.l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
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},
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[MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_2, .start = 0, .end = 31,
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.l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
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},
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[MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_IPV6_SRC_OUT_3, .start = 0, .end = 31,
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.l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
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},
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[MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_0, .start = 0, .end = 31,
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.l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
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},
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[MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_1, .start = 0, .end = 31,
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.l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
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},
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[MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_2, .start = 0, .end = 31,
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.l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
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},
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[MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_IPV6_DST_OUT_3, .start = 0, .end = 31,
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.l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV6,
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},
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[MLX5_ACTION_IN_FIELD_OUT_SIPV4] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_IPV4_OUT_0, .start = 0, .end = 31,
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.l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV4,
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},
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[MLX5_ACTION_IN_FIELD_OUT_DIPV4] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_IPV4_OUT_1, .start = 0, .end = 31,
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.l3_type = DR_STE_ACTION_MDFY_TYPE_L3_IPV4,
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},
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[MLX5_ACTION_IN_FIELD_METADATA_REG_A] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_GNRL_PURPOSE, .start = 0, .end = 31,
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},
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[MLX5_ACTION_IN_FIELD_METADATA_REG_B] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_METADATA_2_CQE, .start = 0, .end = 31,
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},
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[MLX5_ACTION_IN_FIELD_METADATA_REG_C_0] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_REGISTER_6, .start = 0, .end = 31,
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},
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[MLX5_ACTION_IN_FIELD_METADATA_REG_C_1] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_REGISTER_7, .start = 0, .end = 31,
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},
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[MLX5_ACTION_IN_FIELD_METADATA_REG_C_2] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_REGISTER_4, .start = 0, .end = 31,
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},
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[MLX5_ACTION_IN_FIELD_METADATA_REG_C_3] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_REGISTER_5, .start = 0, .end = 31,
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},
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[MLX5_ACTION_IN_FIELD_METADATA_REG_C_4] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_REGISTER_2, .start = 0, .end = 31,
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},
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[MLX5_ACTION_IN_FIELD_METADATA_REG_C_5] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_REGISTER_3, .start = 0, .end = 31,
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},
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[MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_TCP_MISC_0, .start = 0, .end = 31,
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},
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[MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_TCP_MISC_1, .start = 0, .end = 31,
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},
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[MLX5_ACTION_IN_FIELD_OUT_FIRST_VID] = {
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.hw_field = DR_STE_V1_ACTION_MDFY_FLD_L2_OUT_2, .start = 0, .end = 15,
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},
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};
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static void dr_ste_v1_set_entry_type(u8 *hw_ste_p, u8 entry_type)
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{
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MLX5_SET(ste_match_bwc_v1, hw_ste_p, entry_format, entry_type);
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@ -476,6 +629,116 @@ static void dr_ste_v1_set_actions_rx(struct mlx5dr_domain *dmn,
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dr_ste_v1_set_hit_addr(last_ste, attr->final_icm_addr, 1);
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}
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static void dr_ste_v1_set_action_set(u8 *d_action,
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u8 hw_field,
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u8 shifter,
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u8 length,
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u32 data)
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{
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shifter += MLX5_MODIFY_HEADER_V1_QW_OFFSET;
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MLX5_SET(ste_double_action_set_v1, d_action, action_id, DR_STE_V1_ACTION_ID_SET);
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MLX5_SET(ste_double_action_set_v1, d_action, destination_dw_offset, hw_field);
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MLX5_SET(ste_double_action_set_v1, d_action, destination_left_shifter, shifter);
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MLX5_SET(ste_double_action_set_v1, d_action, destination_length, length);
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MLX5_SET(ste_double_action_set_v1, d_action, inline_data, data);
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}
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static void dr_ste_v1_set_action_add(u8 *d_action,
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u8 hw_field,
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u8 shifter,
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u8 length,
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u32 data)
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{
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shifter += MLX5_MODIFY_HEADER_V1_QW_OFFSET;
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MLX5_SET(ste_double_action_add_v1, d_action, action_id, DR_STE_V1_ACTION_ID_ADD);
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MLX5_SET(ste_double_action_add_v1, d_action, destination_dw_offset, hw_field);
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MLX5_SET(ste_double_action_add_v1, d_action, destination_left_shifter, shifter);
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MLX5_SET(ste_double_action_add_v1, d_action, destination_length, length);
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MLX5_SET(ste_double_action_add_v1, d_action, add_value, data);
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}
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static void dr_ste_v1_set_action_copy(u8 *d_action,
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u8 dst_hw_field,
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u8 dst_shifter,
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u8 dst_len,
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u8 src_hw_field,
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u8 src_shifter)
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{
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dst_shifter += MLX5_MODIFY_HEADER_V1_QW_OFFSET;
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src_shifter += MLX5_MODIFY_HEADER_V1_QW_OFFSET;
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MLX5_SET(ste_double_action_copy_v1, d_action, action_id, DR_STE_V1_ACTION_ID_COPY);
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MLX5_SET(ste_double_action_copy_v1, d_action, destination_dw_offset, dst_hw_field);
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MLX5_SET(ste_double_action_copy_v1, d_action, destination_left_shifter, dst_shifter);
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MLX5_SET(ste_double_action_copy_v1, d_action, destination_length, dst_len);
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MLX5_SET(ste_double_action_copy_v1, d_action, source_dw_offset, src_hw_field);
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MLX5_SET(ste_double_action_copy_v1, d_action, source_right_shifter, src_shifter);
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}
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#define DR_STE_DECAP_L3_ACTION_NUM 8
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#define DR_STE_L2_HDR_MAX_SZ 20
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static int dr_ste_v1_set_action_decap_l3_list(void *data,
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u32 data_sz,
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u8 *hw_action,
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u32 hw_action_sz,
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u16 *used_hw_action_num)
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{
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u8 padded_data[DR_STE_L2_HDR_MAX_SZ] = {};
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void *data_ptr = padded_data;
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u16 used_actions = 0;
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u32 inline_data_sz;
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u32 i;
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if (hw_action_sz / DR_STE_ACTION_DOUBLE_SZ < DR_STE_DECAP_L3_ACTION_NUM)
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return -EINVAL;
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memcpy(padded_data, data, data_sz);
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/* Remove L2L3 outer headers */
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MLX5_SET(ste_single_action_remove_header_v1, hw_action, action_id,
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DR_STE_V1_ACTION_ID_REMOVE_HEADER_TO_HEADER);
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MLX5_SET(ste_single_action_remove_header_v1, hw_action, decap, 1);
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MLX5_SET(ste_single_action_remove_header_v1, hw_action, vni_to_cqe, 1);
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MLX5_SET(ste_single_action_remove_header_v1, hw_action, end_anchor,
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DR_STE_HEADER_ANCHOR_INNER_IPV6_IPV4);
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hw_action += DR_STE_ACTION_DOUBLE_SZ;
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used_actions++; /* Remove and NOP are a single double action */
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inline_data_sz =
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MLX5_FLD_SZ_BYTES(ste_double_action_insert_with_inline_v1, inline_data);
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/* Add the new header inline + 2 extra bytes */
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for (i = 0; i < data_sz / inline_data_sz + 1; i++) {
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void *addr_inline;
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MLX5_SET(ste_double_action_insert_with_inline_v1, hw_action, action_id,
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DR_STE_V1_ACTION_ID_INSERT_INLINE);
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/* The hardware expects here offset to words (2 bytes) */
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MLX5_SET(ste_double_action_insert_with_inline_v1, hw_action, start_offset,
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i * 2);
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/* Copy bytes one by one to avoid endianness problem */
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addr_inline = MLX5_ADDR_OF(ste_double_action_insert_with_inline_v1,
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hw_action, inline_data);
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memcpy(addr_inline, data_ptr, inline_data_sz);
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hw_action += DR_STE_ACTION_DOUBLE_SZ;
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data_ptr += inline_data_sz;
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used_actions++;
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}
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/* Remove 2 extra bytes */
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MLX5_SET(ste_single_action_remove_header_size_v1, hw_action, action_id,
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DR_STE_V1_ACTION_ID_REMOVE_BY_SIZE);
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MLX5_SET(ste_single_action_remove_header_size_v1, hw_action, start_offset, data_sz / 2);
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/* The hardware expects here size in words (2 bytes) */
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MLX5_SET(ste_single_action_remove_header_size_v1, hw_action, remove_size, 1);
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used_actions++;
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*used_hw_action_num = used_actions;
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return 0;
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}
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static void dr_ste_v1_build_eth_l2_src_dst_bit_mask(struct mlx5dr_match_param *value,
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bool inner, u8 *bit_mask)
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{
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@ -1339,4 +1602,10 @@ struct mlx5dr_ste_ctx ste_ctx_v1 = {
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/* Actions */
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.set_actions_rx = &dr_ste_v1_set_actions_rx,
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.set_actions_tx = &dr_ste_v1_set_actions_tx,
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.modify_field_arr_sz = ARRAY_SIZE(dr_ste_v1_action_modify_field_arr),
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.modify_field_arr = dr_ste_v1_action_modify_field_arr,
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.set_action_set = &dr_ste_v1_set_action_set,
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.set_action_add = &dr_ste_v1_set_action_add,
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.set_action_copy = &dr_ste_v1_set_action_copy,
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.set_action_decap_l3_list = &dr_ste_v1_set_action_decap_l3_list,
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};
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@ -4,6 +4,10 @@
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#ifndef MLX5_IFC_DR_STE_V1_H
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#define MLX5_IFC_DR_STE_V1_H
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enum mlx5_ifc_ste_v1_modify_hdr_offset {
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MLX5_MODIFY_HEADER_V1_QW_OFFSET = 0x20,
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};
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struct mlx5_ifc_ste_single_action_flow_tag_v1_bits {
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u8 action_id[0x8];
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u8 flow_tag[0x18];
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