drm/amdgpu: use the new VM backend for PTEs
And remove the existing code when it is unused. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Christian König
Alex Deucher
Родитель
e6899d5590
Коммит
c354669583
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@ -1170,66 +1170,6 @@ struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
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return NULL;
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}
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/**
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* amdgpu_vm_do_set_ptes - helper to call the right asic function
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*
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* @params: see amdgpu_vm_update_params definition
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* @bo: PD/PT to update
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* @pe: addr of the page entry
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* @addr: dst addr to write into pe
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* @count: number of page entries to update
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* @incr: increase next addr by incr bytes
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* @flags: hw access flags
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*
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* Traces the parameters and calls the right asic functions
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* to setup the page table using the DMA.
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*/
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static void amdgpu_vm_do_set_ptes(struct amdgpu_vm_update_params *params,
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struct amdgpu_bo *bo,
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uint64_t pe, uint64_t addr,
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unsigned count, uint32_t incr,
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uint64_t flags)
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{
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pe += amdgpu_bo_gpu_offset(bo);
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trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
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if (count < 3) {
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amdgpu_vm_write_pte(params->adev, params->ib, pe,
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addr | flags, count, incr);
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} else {
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amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr,
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count, incr, flags);
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}
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}
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/**
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* amdgpu_vm_do_copy_ptes - copy the PTEs from the GART
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*
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* @params: see amdgpu_vm_update_params definition
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* @bo: PD/PT to update
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* @pe: addr of the page entry
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* @addr: dst addr to write into pe
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* @count: number of page entries to update
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* @incr: increase next addr by incr bytes
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* @flags: hw access flags
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*
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* Traces the parameters and calls the DMA function to copy the PTEs.
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*/
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static void amdgpu_vm_do_copy_ptes(struct amdgpu_vm_update_params *params,
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struct amdgpu_bo *bo,
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uint64_t pe, uint64_t addr,
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unsigned count, uint32_t incr,
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uint64_t flags)
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{
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uint64_t src = (params->src + (addr >> 12) * 8);
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pe += amdgpu_bo_gpu_offset(bo);
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trace_amdgpu_vm_copy_ptes(pe, src, count);
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amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count);
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}
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/**
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* amdgpu_vm_map_gart - Resolve gart mapping of addr
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*
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@ -1257,58 +1197,6 @@ uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
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return result;
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}
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/**
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* amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU
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*
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* @params: see amdgpu_vm_update_params definition
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* @bo: PD/PT to update
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* @pe: kmap addr of the page entry
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* @addr: dst addr to write into pe
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* @count: number of page entries to update
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* @incr: increase next addr by incr bytes
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* @flags: hw access flags
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*
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* Write count number of PT/PD entries directly.
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*/
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static void amdgpu_vm_cpu_set_ptes(struct amdgpu_vm_update_params *params,
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struct amdgpu_bo *bo,
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uint64_t pe, uint64_t addr,
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unsigned count, uint32_t incr,
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uint64_t flags)
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{
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unsigned int i;
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uint64_t value;
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pe += (unsigned long)amdgpu_bo_kptr(bo);
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trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
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for (i = 0; i < count; i++) {
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value = params->pages_addr ?
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amdgpu_vm_map_gart(params->pages_addr, addr) :
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addr;
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amdgpu_gmc_set_pte_pde(params->adev, (void *)(uintptr_t)pe,
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i, value, flags);
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addr += incr;
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}
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}
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/**
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* amdgpu_vm_update_func - helper to call update function
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*
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* Calls the update function for both the given BO as well as its shadow.
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*/
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static void amdgpu_vm_update_func(struct amdgpu_vm_update_params *params,
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struct amdgpu_bo *bo,
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uint64_t pe, uint64_t addr,
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unsigned count, uint32_t incr,
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uint64_t flags)
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{
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if (bo->shadow)
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params->func(params, bo->shadow, pe, addr, count, incr, flags);
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params->func(params, bo, pe, addr, count, incr, flags);
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}
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/*
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* amdgpu_vm_update_pde - update a single level in the hierarchy
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*
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@ -1434,7 +1322,8 @@ static void amdgpu_vm_update_flags(struct amdgpu_vm_update_params *params,
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flags |= AMDGPU_PTE_EXECUTABLE;
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}
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amdgpu_vm_update_func(params, bo, pe, addr, count, incr, flags);
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params->vm->update_funcs->update(params, bo, pe, addr, count, incr,
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flags);
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}
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/**
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@ -1651,12 +1540,8 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
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uint64_t flags, uint64_t addr,
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struct dma_fence **fence)
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{
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struct amdgpu_ring *ring;
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void *owner = AMDGPU_FENCE_OWNER_VM;
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unsigned nptes, ncmds, ndw;
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struct amdgpu_job *job;
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struct amdgpu_vm_update_params params;
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struct dma_fence *f = NULL;
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void *owner = AMDGPU_FENCE_OWNER_VM;
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int r;
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memset(¶ms, 0, sizeof(params));
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@ -1668,116 +1553,15 @@ static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
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if (!(flags & AMDGPU_PTE_VALID))
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owner = AMDGPU_FENCE_OWNER_KFD;
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if (vm->use_cpu_for_update) {
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/* Wait for PT BOs to be idle. PTs share the same resv. object
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* as the root PD BO
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*/
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r = amdgpu_bo_sync_wait(vm->root.base.bo, owner, true);
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if (unlikely(r))
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return r;
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/* Wait for any BO move to be completed */
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if (exclusive) {
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r = dma_fence_wait(exclusive, true);
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if (unlikely(r))
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return r;
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}
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params.func = amdgpu_vm_cpu_set_ptes;
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return amdgpu_vm_update_ptes(¶ms, start, last + 1,
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addr, flags);
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}
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ring = container_of(vm->entity.rq->sched, struct amdgpu_ring, sched);
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nptes = last - start + 1;
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/*
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* reserve space for two commands every (1 << BLOCK_SIZE)
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* entries or 2k dwords (whatever is smaller)
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*/
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ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1);
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/* The second command is for the shadow pagetables. */
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if (vm->root.base.bo->shadow)
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ncmds *= 2;
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/* padding, etc. */
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ndw = 64;
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if (pages_addr) {
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/* copy commands needed */
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ndw += ncmds * adev->vm_manager.vm_pte_funcs->copy_pte_num_dw;
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/* and also PTEs */
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ndw += nptes * 2;
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params.func = amdgpu_vm_do_copy_ptes;
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} else {
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/* set page commands needed */
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ndw += ncmds * 10;
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/* extra commands for begin/end fragments */
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ncmds = 2 * adev->vm_manager.fragment_size;
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if (vm->root.base.bo->shadow)
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ncmds *= 2;
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ndw += 10 * ncmds;
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params.func = amdgpu_vm_do_set_ptes;
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}
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r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
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r = vm->update_funcs->prepare(¶ms, owner, exclusive);
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if (r)
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return r;
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params.ib = &job->ibs[0];
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if (pages_addr) {
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uint64_t *pte;
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unsigned i;
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/* Put the PTEs at the end of the IB. */
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i = ndw - nptes * 2;
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pte= (uint64_t *)&(job->ibs->ptr[i]);
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params.src = job->ibs->gpu_addr + i * 4;
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for (i = 0; i < nptes; ++i) {
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pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i *
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AMDGPU_GPU_PAGE_SIZE);
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pte[i] |= flags;
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}
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addr = 0;
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}
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r = amdgpu_sync_fence(adev, &job->sync, exclusive, false);
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if (r)
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goto error_free;
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r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv,
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owner, false);
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if (r)
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goto error_free;
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r = amdgpu_vm_update_ptes(¶ms, start, last + 1, addr, flags);
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if (r)
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goto error_free;
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return r;
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amdgpu_ring_pad_ib(ring, params.ib);
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WARN_ON(params.ib->length_dw > ndw);
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r = amdgpu_job_submit(job, &vm->entity, AMDGPU_FENCE_OWNER_VM, &f);
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if (r)
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goto error_free;
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amdgpu_bo_fence(vm->root.base.bo, f, true);
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dma_fence_put(*fence);
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*fence = f;
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return 0;
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error_free:
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amdgpu_job_free(job);
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return r;
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return vm->update_funcs->commit(¶ms, fence);
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}
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/**
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@ -1860,7 +1644,6 @@ static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
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if (pages_addr) {
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uint64_t count;
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max_entries = min(max_entries, 16ull * 1024ull);
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for (count = 1;
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count < max_entries / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
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++count) {
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@ -198,11 +198,6 @@ struct amdgpu_vm_update_params {
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*/
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dma_addr_t *pages_addr;
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/**
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* @src: address where to copy page table entries from
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*/
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uint64_t src;
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/**
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* @job: job to used for hw submission
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*/
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@ -217,14 +212,6 @@ struct amdgpu_vm_update_params {
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* @num_dw_left: number of dw left for the IB
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*/
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unsigned int num_dw_left;
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/**
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* @func: Function which actually does the update
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*/
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void (*func)(struct amdgpu_vm_update_params *params,
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struct amdgpu_bo *bo, uint64_t pe,
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uint64_t addr, unsigned count, uint32_t incr,
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uint64_t flags);
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};
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struct amdgpu_vm_update_funcs {
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