drm/nouveau/bios: parse older ramcfg/timing data like we do newer ones
Done after discussion with Roy. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
Родитель
a407318913
Коммит
c378eb7461
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@ -8,76 +8,114 @@ struct nvbios_ramcfg {
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unsigned rammap_hdr;
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unsigned rammap_min;
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unsigned rammap_max;
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unsigned rammap_11_08_01:1;
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unsigned rammap_11_08_0c:2;
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unsigned rammap_11_08_10:1;
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unsigned rammap_11_09_01ff:9;
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unsigned rammap_11_0a_03fe:9;
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unsigned rammap_11_0a_0400:1;
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unsigned rammap_11_0a_0800:1;
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unsigned rammap_11_0b_01f0:5;
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unsigned rammap_11_0b_0200:1;
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unsigned rammap_11_0b_0400:1;
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unsigned rammap_11_0b_0800:1;
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unsigned rammap_11_0d:8;
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unsigned rammap_11_0e:8;
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unsigned rammap_11_0f:8;
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unsigned rammap_11_11_0c:2;
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union {
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struct {
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unsigned rammap_10_04_02:1;
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unsigned rammap_10_04_08:1;
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};
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struct {
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unsigned rammap_11_08_01:1;
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unsigned rammap_11_08_0c:2;
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unsigned rammap_11_08_10:1;
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unsigned rammap_11_09_01ff:9;
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unsigned rammap_11_0a_03fe:9;
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unsigned rammap_11_0a_0400:1;
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unsigned rammap_11_0a_0800:1;
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unsigned rammap_11_0b_01f0:5;
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unsigned rammap_11_0b_0200:1;
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unsigned rammap_11_0b_0400:1;
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unsigned rammap_11_0b_0800:1;
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unsigned rammap_11_0d:8;
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unsigned rammap_11_0e:8;
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unsigned rammap_11_0f:8;
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unsigned rammap_11_11_0c:2;
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};
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};
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unsigned ramcfg_ver;
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unsigned ramcfg_hdr;
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unsigned ramcfg_timing;
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unsigned ramcfg_11_01_01:1;
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unsigned ramcfg_11_01_02:1;
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unsigned ramcfg_11_01_04:1;
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unsigned ramcfg_11_01_08:1;
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unsigned ramcfg_11_01_10:1;
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unsigned ramcfg_11_01_20:1;
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unsigned ramcfg_11_01_40:1;
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unsigned ramcfg_11_01_80:1;
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unsigned ramcfg_11_02_03:2;
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unsigned ramcfg_11_02_04:1;
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unsigned ramcfg_11_02_08:1;
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unsigned ramcfg_11_02_10:1;
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unsigned ramcfg_11_02_40:1;
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unsigned ramcfg_11_02_80:1;
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unsigned ramcfg_11_03_0f:4;
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unsigned ramcfg_11_03_30:2;
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unsigned ramcfg_11_03_c0:2;
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unsigned ramcfg_11_03_f0:4;
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unsigned ramcfg_11_04:8;
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unsigned ramcfg_11_06:8;
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unsigned ramcfg_11_07_02:1;
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unsigned ramcfg_11_07_04:1;
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unsigned ramcfg_11_07_08:1;
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unsigned ramcfg_11_07_10:1;
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unsigned ramcfg_11_07_40:1;
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unsigned ramcfg_11_07_80:1;
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unsigned ramcfg_11_08_01:1;
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unsigned ramcfg_11_08_02:1;
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unsigned ramcfg_11_08_04:1;
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unsigned ramcfg_11_08_08:1;
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unsigned ramcfg_11_08_10:1;
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unsigned ramcfg_11_08_20:1;
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unsigned ramcfg_11_09:8;
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union {
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struct {
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unsigned ramcfg_10_02_01:1;
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unsigned ramcfg_10_02_02:1;
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unsigned ramcfg_10_02_04:1;
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unsigned ramcfg_10_02_08:1;
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unsigned ramcfg_10_02_10:1;
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unsigned ramcfg_10_02_20:1;
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unsigned ramcfg_10_02_40:1;
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unsigned ramcfg_10_03_0f:4;
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unsigned ramcfg_10_05:8;
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unsigned ramcfg_10_06:8;
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unsigned ramcfg_10_07:8;
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unsigned ramcfg_10_08:8;
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unsigned ramcfg_10_09_0f:4;
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unsigned ramcfg_10_09_f0:4;
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};
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struct {
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unsigned ramcfg_11_01_01:1;
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unsigned ramcfg_11_01_02:1;
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unsigned ramcfg_11_01_04:1;
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unsigned ramcfg_11_01_08:1;
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unsigned ramcfg_11_01_10:1;
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unsigned ramcfg_11_01_20:1;
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unsigned ramcfg_11_01_40:1;
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unsigned ramcfg_11_01_80:1;
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unsigned ramcfg_11_02_03:2;
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unsigned ramcfg_11_02_04:1;
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unsigned ramcfg_11_02_08:1;
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unsigned ramcfg_11_02_10:1;
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unsigned ramcfg_11_02_40:1;
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unsigned ramcfg_11_02_80:1;
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unsigned ramcfg_11_03_0f:4;
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unsigned ramcfg_11_03_30:2;
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unsigned ramcfg_11_03_c0:2;
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unsigned ramcfg_11_03_f0:4;
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unsigned ramcfg_11_04:8;
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unsigned ramcfg_11_06:8;
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unsigned ramcfg_11_07_02:1;
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unsigned ramcfg_11_07_04:1;
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unsigned ramcfg_11_07_08:1;
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unsigned ramcfg_11_07_10:1;
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unsigned ramcfg_11_07_40:1;
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unsigned ramcfg_11_07_80:1;
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unsigned ramcfg_11_08_01:1;
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unsigned ramcfg_11_08_02:1;
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unsigned ramcfg_11_08_04:1;
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unsigned ramcfg_11_08_08:1;
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unsigned ramcfg_11_08_10:1;
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unsigned ramcfg_11_08_20:1;
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unsigned ramcfg_11_09:8;
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};
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};
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unsigned timing_ver;
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unsigned timing_hdr;
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unsigned timing[11];
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unsigned timing_20_2e_03:2;
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unsigned timing_20_2e_30:2;
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unsigned timing_20_2e_c0:2;
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unsigned timing_20_2f_03:2;
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unsigned timing_20_2c_003f:6;
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unsigned timing_20_2c_1fc0:7;
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unsigned timing_20_30_f8:5;
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unsigned timing_20_30_07:3;
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unsigned timing_20_31_0007:3;
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unsigned timing_20_31_0078:4;
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unsigned timing_20_31_0780:4;
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unsigned timing_20_31_0800:1;
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unsigned timing_20_31_7000:3;
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unsigned timing_20_31_8000:1;
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union {
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struct {
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unsigned timing_10_WR:8;
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unsigned timing_10_CL:8;
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unsigned timing_10_ODT:3;
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unsigned timing_10_CWL:8;
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};
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struct {
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unsigned timing_20_2e_03:2;
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unsigned timing_20_2e_30:2;
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unsigned timing_20_2e_c0:2;
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unsigned timing_20_2f_03:2;
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unsigned timing_20_2c_003f:6;
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unsigned timing_20_2c_1fc0:7;
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unsigned timing_20_30_f8:5;
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unsigned timing_20_30_07:3;
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unsigned timing_20_31_0007:3;
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unsigned timing_20_31_0078:4;
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unsigned timing_20_31_0780:4;
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unsigned timing_20_31_0800:1;
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unsigned timing_20_31_7000:3;
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unsigned timing_20_31_8000:1;
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};
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};
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};
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u8 nvbios_ramcfg_count(struct nouveau_bios *);
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@ -146,11 +146,6 @@ struct nouveau_ram {
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int (*calc)(struct nouveau_fb *, u32 freq);
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int (*prog)(struct nouveau_fb *);
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void (*tidy)(struct nouveau_fb *);
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struct {
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u8 version;
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u32 data;
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u8 size;
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} rammap, ramcfg, timing;
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u32 freq;
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u32 mr[16];
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u32 mr1_nuts;
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@ -87,6 +87,8 @@ nvbios_rammapEp(struct nouveau_bios *bios, int idx,
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case 0x10:
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p->rammap_min = nv_ro16(bios, data + 0x00);
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p->rammap_max = nv_ro16(bios, data + 0x02);
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p->rammap_10_04_02 = (nv_ro08(bios, data + 0x04) & 0x02) >> 1;
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p->rammap_10_04_08 = (nv_ro08(bios, data + 0x04) & 0x08) >> 3;
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break;
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case 0x11:
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p->rammap_min = nv_ro16(bios, data + 0x00);
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@ -152,6 +154,23 @@ nvbios_rammapSp(struct nouveau_bios *bios, u32 data,
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p->ramcfg_ver = *ver;
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p->ramcfg_hdr = *hdr;
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switch (!!data * *ver) {
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case 0x10:
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p->ramcfg_timing = nv_ro08(bios, data + 0x01);
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p->ramcfg_10_02_01 = (nv_ro08(bios, data + 0x02) & 0x01) >> 0;
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p->ramcfg_10_02_02 = (nv_ro08(bios, data + 0x02) & 0x02) >> 1;
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p->ramcfg_10_02_04 = (nv_ro08(bios, data + 0x02) & 0x04) >> 2;
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p->ramcfg_10_02_08 = (nv_ro08(bios, data + 0x02) & 0x08) >> 3;
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p->ramcfg_10_02_10 = (nv_ro08(bios, data + 0x02) & 0x10) >> 4;
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p->ramcfg_10_02_20 = (nv_ro08(bios, data + 0x02) & 0x20) >> 5;
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p->ramcfg_10_02_40 = (nv_ro08(bios, data + 0x02) & 0x40) >> 6;
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p->ramcfg_10_03_0f = (nv_ro08(bios, data + 0x03) & 0x0f) >> 0;
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p->ramcfg_10_05 = (nv_ro08(bios, data + 0x05) & 0xff) >> 0;
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p->ramcfg_10_06 = (nv_ro08(bios, data + 0x06) & 0xff) >> 0;
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p->ramcfg_10_07 = (nv_ro08(bios, data + 0x07) & 0xff) >> 0;
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p->ramcfg_10_08 = (nv_ro08(bios, data + 0x08) & 0xff) >> 0;
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p->ramcfg_10_09_0f = (nv_ro08(bios, data + 0x09) & 0x0f) >> 0;
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p->ramcfg_10_09_f0 = (nv_ro08(bios, data + 0x09) & 0xf0) >> 4;
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break;
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case 0x11:
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p->ramcfg_timing = nv_ro08(bios, data + 0x00);
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p->ramcfg_11_01_01 = (nv_ro08(bios, data + 0x01) & 0x01) >> 0;
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@ -92,6 +92,12 @@ nvbios_timingEp(struct nouveau_bios *bios, int idx,
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p->timing_ver = *ver;
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p->timing_hdr = *hdr;
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switch (!!data * *ver) {
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case 0x10:
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p->timing_10_WR = nv_ro08(bios, data + 0x00);
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p->timing_10_CL = nv_ro08(bios, data + 0x02);
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p->timing_10_ODT = nv_ro08(bios, data + 0x0e) & 0x07;
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p->timing_10_CWL = nv_ro08(bios, data + 0x13);
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break;
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case 0x20:
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p->timing[0] = nv_ro32(bios, data + 0x00);
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p->timing[1] = nv_ro32(bios, data + 0x04);
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@ -79,21 +79,27 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
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struct nva3_ram *ram = (void *)pfb->ram;
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struct nva3_ramfuc *fuc = &ram->fuc;
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struct nva3_clock_info mclk;
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struct nvbios_ramcfg cfg;
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u8 ver, cnt, len, strap;
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struct nouveau_ram_data *next;
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u8 ver, hdr, cnt, len, strap;
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u32 data;
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struct {
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u32 data;
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u8 size;
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} rammap, ramcfg, timing;
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u32 r004018, r100760, ctrl;
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u32 unk714, unk718, unk71c;
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int ret;
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int ret, i;
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next = &ram->base.target;
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next->freq = freq;
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ram->base.next = next;
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/* lookup memory config data relevant to the target frequency */
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rammap.data = nvbios_rammapEm(bios, freq / 1000, &ver, &rammap.size,
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&cnt, &ramcfg.size, &cfg);
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if (!rammap.data || ver != 0x10 || rammap.size < 0x0e) {
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i = 0;
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while ((data = nvbios_rammapEp(bios, i++, &ver, &hdr, &cnt, &len,
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&next->bios))) {
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if (freq / 1000 >= next->bios.rammap_min &&
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freq / 1000 <= next->bios.rammap_max)
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break;
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}
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if (!data || ver != 0x10 || hdr < 0x0e) {
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nv_error(pfb, "invalid/missing rammap entry\n");
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return -EINVAL;
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}
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@ -105,23 +111,22 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
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return -EINVAL;
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}
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ramcfg.data = rammap.data + rammap.size + (strap * ramcfg.size);
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if (!ramcfg.data || ver != 0x10 || ramcfg.size < 0x0e) {
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data = nvbios_rammapSp(bios, data, ver, hdr, cnt, len, strap,
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&ver, &hdr, &next->bios);
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if (!data || ver != 0x10 || hdr < 0x0e) {
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nv_error(pfb, "invalid/missing ramcfg entry\n");
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return -EINVAL;
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}
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/* lookup memory timings, if bios says they're present */
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strap = nv_ro08(bios, ramcfg.data + 0x01);
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if (strap != 0xff) {
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timing.data = nvbios_timingEe(bios, strap, &ver, &timing.size,
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&cnt, &len);
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if (!timing.data || ver != 0x10 || timing.size < 0x19) {
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if (next->bios.ramcfg_timing != 0xff) {
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data = nvbios_timingEp(bios, next->bios.ramcfg_timing,
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&ver, &hdr, &cnt, &len,
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&next->bios);
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if (!data || ver != 0x10 || hdr < 0x19) {
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nv_error(pfb, "invalid/missing timing entry\n");
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return -EINVAL;
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}
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} else {
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timing.data = 0;
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}
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ret = nva3_pll_info(nouveau_clock(pfb), 0x12, 0x4000, freq, &mclk);
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@ -164,17 +169,17 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
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ram_mask(fuc, 0x004168, 0x003f3141, ctrl);
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}
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if ( (nv_ro08(bios, ramcfg.data + 0x02) & 0x10)) {
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if (next->bios.ramcfg_10_02_10) {
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ram_mask(fuc, 0x111104, 0x00000600, 0x00000000);
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} else {
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ram_mask(fuc, 0x111100, 0x40000000, 0x40000000);
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ram_mask(fuc, 0x111104, 0x00000180, 0x00000000);
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}
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if (!(nv_ro08(bios, rammap.data + 0x04) & 0x02))
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if (!next->bios.rammap_10_04_02)
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ram_mask(fuc, 0x100200, 0x00000800, 0x00000000);
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ram_wr32(fuc, 0x611200, 0x00003300);
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if (!(nv_ro08(bios, ramcfg.data + 0x02) & 0x10))
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if (!next->bios.ramcfg_10_02_10)
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ram_wr32(fuc, 0x111100, 0x4c020000); /*XXX*/
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ram_wr32(fuc, 0x1002d4, 0x00000001);
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@ -203,17 +208,16 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
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ram_wr32(fuc, 0x004018, 0x0000d000 | r004018);
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}
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if ( (nv_ro08(bios, rammap.data + 0x04) & 0x08)) {
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u32 unk5a0 = (nv_ro16(bios, ramcfg.data + 0x05) << 8) |
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nv_ro08(bios, ramcfg.data + 0x05);
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u32 unk5a4 = (nv_ro16(bios, ramcfg.data + 0x07));
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u32 unk804 = (nv_ro08(bios, ramcfg.data + 0x09) & 0xf0) << 16 |
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(nv_ro08(bios, ramcfg.data + 0x03) & 0x0f) << 16 |
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(nv_ro08(bios, ramcfg.data + 0x09) & 0x0f) |
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0x80000000;
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ram_wr32(fuc, 0x1005a0, unk5a0);
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ram_wr32(fuc, 0x1005a4, unk5a4);
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ram_wr32(fuc, 0x10f804, unk804);
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if (next->bios.rammap_10_04_08) {
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ram_wr32(fuc, 0x1005a0, next->bios.ramcfg_10_06 << 16 |
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next->bios.ramcfg_10_05 << 8 |
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next->bios.ramcfg_10_05);
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ram_wr32(fuc, 0x1005a4, next->bios.ramcfg_10_08 << 8 |
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next->bios.ramcfg_10_07);
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ram_wr32(fuc, 0x10f804, next->bios.ramcfg_10_09_f0 << 20 |
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next->bios.ramcfg_10_03_0f << 16 |
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next->bios.ramcfg_10_09_0f |
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0x80000000);
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ram_mask(fuc, 0x10053c, 0x00001000, 0x00000000);
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} else {
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ram_mask(fuc, 0x10053c, 0x00001000, 0x00001000);
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@ -251,27 +255,26 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
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ram_mask(fuc, 0x100220[0], 0x00000000, 0x00000000);
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ram_mask(fuc, 0x100220[8], 0x00000000, 0x00000000);
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data = (nv_ro08(bios, ramcfg.data + 0x02) & 0x08) ? 0x00000000 : 0x00001000;
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ram_mask(fuc, 0x100200, 0x00001000, data);
|
||||
ram_mask(fuc, 0x100200, 0x00001000, !next->bios.ramcfg_10_02_08 << 12);
|
||||
|
||||
unk714 = ram_rd32(fuc, 0x100714) & ~0xf0000010;
|
||||
unk718 = ram_rd32(fuc, 0x100718) & ~0x00000100;
|
||||
unk71c = ram_rd32(fuc, 0x10071c) & ~0x00000100;
|
||||
if ( (nv_ro08(bios, ramcfg.data + 0x02) & 0x20))
|
||||
if (next->bios.ramcfg_10_02_20)
|
||||
unk714 |= 0xf0000000;
|
||||
if (!(nv_ro08(bios, ramcfg.data + 0x02) & 0x04))
|
||||
if (!next->bios.ramcfg_10_02_04)
|
||||
unk714 |= 0x00000010;
|
||||
ram_wr32(fuc, 0x100714, unk714);
|
||||
|
||||
if (nv_ro08(bios, ramcfg.data + 0x02) & 0x01)
|
||||
if (next->bios.ramcfg_10_02_01)
|
||||
unk71c |= 0x00000100;
|
||||
ram_wr32(fuc, 0x10071c, unk71c);
|
||||
|
||||
if (nv_ro08(bios, ramcfg.data + 0x02) & 0x02)
|
||||
if (next->bios.ramcfg_10_02_02)
|
||||
unk718 |= 0x00000100;
|
||||
ram_wr32(fuc, 0x100718, unk718);
|
||||
|
||||
if (nv_ro08(bios, ramcfg.data + 0x02) & 0x10)
|
||||
if (next->bios.ramcfg_10_02_10)
|
||||
ram_wr32(fuc, 0x111100, 0x48000000); /*XXX*/
|
||||
|
||||
ram_mask(fuc, mr[0], 0x100, 0x100);
|
||||
|
|
@ -283,9 +286,9 @@ nva3_ram_calc(struct nouveau_fb *pfb, u32 freq)
|
|||
ram_nsec(fuc, 12000);
|
||||
|
||||
ram_wr32(fuc, 0x611200, 0x00003330);
|
||||
if ( (nv_ro08(bios, rammap.data + 0x04) & 0x02))
|
||||
if (next->bios.rammap_10_04_02)
|
||||
ram_mask(fuc, 0x100200, 0x00000800, 0x00000800);
|
||||
if ( (nv_ro08(bios, ramcfg.data + 0x02) & 0x10)) {
|
||||
if (next->bios.ramcfg_10_02_10) {
|
||||
ram_mask(fuc, 0x111104, 0x00000180, 0x00000180);
|
||||
ram_mask(fuc, 0x111100, 0x40000000, 0x00000000);
|
||||
} else {
|
||||
|
|
|
|||
|
|
@ -23,7 +23,6 @@
|
|||
* Ben Skeggs
|
||||
*/
|
||||
|
||||
#include <subdev/bios.h>
|
||||
#include "priv.h"
|
||||
|
||||
struct ramxlat {
|
||||
|
|
@ -61,19 +60,18 @@ ramddr2_wr[] = {
|
|||
int
|
||||
nouveau_sddr2_calc(struct nouveau_ram *ram)
|
||||
{
|
||||
struct nouveau_bios *bios = nouveau_bios(ram);
|
||||
int CL, WR, DLL = 0, ODT = 0;
|
||||
|
||||
switch (!!ram->timing.data * ram->timing.version) {
|
||||
switch (ram->next->bios.timing_ver) {
|
||||
case 0x10:
|
||||
CL = nv_ro08(bios, ram->timing.data + 0x02);
|
||||
WR = nv_ro08(bios, ram->timing.data + 0x00);
|
||||
DLL = !(nv_ro08(bios, ram->ramcfg.data + 0x02) & 0x40);
|
||||
ODT = nv_ro08(bios, ram->timing.data + 0x0e) & 0x03;
|
||||
CL = ram->next->bios.timing_10_CL;
|
||||
WR = ram->next->bios.timing_10_WR;
|
||||
DLL = !ram->next->bios.ramcfg_10_02_40;
|
||||
ODT = ram->next->bios.timing_10_ODT & 3;
|
||||
break;
|
||||
case 0x20:
|
||||
CL = nv_ro08(bios, ram->timing.data + 0x04) & 0x1f;
|
||||
WR = nv_ro08(bios, ram->timing.data + 0x0a) & 0x7f;
|
||||
CL = (ram->next->bios.timing[1] & 0x0000001f);
|
||||
WR = (ram->next->bios.timing[2] & 0x007f0000) >> 16;
|
||||
break;
|
||||
default:
|
||||
return -ENOSYS;
|
||||
|
|
|
|||
|
|
@ -23,7 +23,6 @@
|
|||
* Roy Spliet <rspliet@eclipso.eu>
|
||||
*/
|
||||
|
||||
#include <subdev/bios.h>
|
||||
#include "priv.h"
|
||||
|
||||
struct ramxlat {
|
||||
|
|
@ -70,25 +69,19 @@ ramddr3_cwl[] = {
|
|||
int
|
||||
nouveau_sddr3_calc(struct nouveau_ram *ram)
|
||||
{
|
||||
struct nouveau_bios *bios = nouveau_bios(ram);
|
||||
int CWL, CL, WR, DLL = 0, ODT = 0;
|
||||
u8 ver;
|
||||
|
||||
ver = !!ram->timing.data * ram->timing.version;
|
||||
if (ram->next)
|
||||
ver = ram->next->bios.timing_ver;
|
||||
|
||||
switch (ver) {
|
||||
switch (ram->next->bios.timing_ver) {
|
||||
case 0x10:
|
||||
if (ram->timing.size < 0x17) {
|
||||
if (ram->next->bios.timing_hdr < 0x17) {
|
||||
/* XXX: NV50: Get CWL from the timing register */
|
||||
return -ENOSYS;
|
||||
}
|
||||
CWL = nv_ro08(bios, ram->timing.data + 0x13);
|
||||
CL = nv_ro08(bios, ram->timing.data + 0x02);
|
||||
WR = nv_ro08(bios, ram->timing.data + 0x00);
|
||||
DLL = !(nv_ro08(bios, ram->ramcfg.data + 0x02) & 0x40);
|
||||
ODT = nv_ro08(bios, ram->timing.data + 0x0e) & 0x07;
|
||||
CWL = ram->next->bios.timing_10_CWL;
|
||||
CL = ram->next->bios.timing_10_CL;
|
||||
WR = ram->next->bios.timing_10_WR;
|
||||
DLL = !ram->next->bios.ramcfg_10_02_40;
|
||||
ODT = ram->next->bios.timing_10_ODT;
|
||||
break;
|
||||
case 0x20:
|
||||
CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7;
|
||||
|
|
|
|||
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