Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/jkirsher/net-next
Jeff Kirsher says: ==================== This series contains updates to e1000e, igb and ixgbe. There are 2 patches in this series which could be applied to net, but since Linus is so very close to releasing 3.9, I do not think it prudent to try and push these into net at this time. I have CC'd stable on these patches so that they can queue them up as soon as 3.9 gets released. The 2 patches are: e1000e: fix numeric overflow in phc settime method ixgbe: fix EICR write in ixgbe_msix_other Richard provides a fix for e1000e by using a helper function from time.h to resolve a unintended overflow in the PTP settime function. Bruce provides a fix to wait for NAPI to be done with the current context after disabling interrupts and then disable NAPI when the interface is going down. This fixes a possible "unable to handle kernel paging request" panic in net-next. Andi Kleen provides a patch for igb to use mdelay instead of udelay when we needed 100000us. Jacob provides a fix for ixgbe to simply mask the lower 16bits off so that ixgbe_msix_other does not write them in the EICR, which causes them to remain high and be properly handled by the clean_rings interrupt routine as normal. Emil cleans up the logic in ixgbe_setup_loopback_test() to only access registers applicable to the MAC type. In addition, removes majority of the AUTOC register reads by using a cached value instead to avoid writing corrupted values to AUTOC due to bad FW. Emil also add support for disabling link during boot time. Lastly, he provides a patch which adds the MAC type to the version in ethtool_regs which will make it easier to check the MAC type when dumping registers with ethtool. There is a separate ethtool tool patch which is dependent upon Emil's last patch of the series to add the MAC type to the version in ethtool_regs, which will be sent separately. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
Коммит
c39904a0ac
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@ -4016,6 +4016,8 @@ void e1000e_down(struct e1000_adapter *adapter)
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e1000_irq_disable(adapter);
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napi_synchronize(&adapter->napi);
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del_timer_sync(&adapter->watchdog_timer);
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del_timer_sync(&adapter->phy_info_timer);
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@ -4372,12 +4374,13 @@ static int e1000_close(struct net_device *netdev)
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pm_runtime_get_sync(&pdev->dev);
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napi_disable(&adapter->napi);
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if (!test_bit(__E1000_DOWN, &adapter->state)) {
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e1000e_down(adapter);
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e1000_free_irq(adapter);
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}
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napi_disable(&adapter->napi);
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e1000_power_down_phy(adapter);
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e1000e_free_tx_resources(adapter->tx_ring);
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@ -145,8 +145,7 @@ static int e1000e_phc_settime(struct ptp_clock_info *ptp,
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unsigned long flags;
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u64 ns;
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ns = ts->tv_sec * NSEC_PER_SEC;
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ns += ts->tv_nsec;
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ns = timespec_to_ns(ts);
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/* reset the timecounter */
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spin_lock_irqsave(&adapter->systim_lock, flags);
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@ -1130,7 +1130,7 @@ s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
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if (phy->autoneg_wait_to_complete) {
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hw_dbg("Waiting for forced speed/duplex link on IGP phy.\n");
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ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
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ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
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if (ret_val)
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goto out;
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@ -1138,7 +1138,7 @@ s32 igb_phy_force_speed_duplex_igp(struct e1000_hw *hw)
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hw_dbg("Link taking longer than expected.\n");
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/* Try once more */
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ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 100000, &link);
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ret_val = igb_phy_has_link(hw, PHY_FORCE_LIMIT, 10000, &link);
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if (ret_val)
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goto out;
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}
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@ -1590,7 +1590,7 @@ s32 igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
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* it across the board.
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*/
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ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
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if (ret_val) {
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if (ret_val && usec_interval > 0) {
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/* If the first read fails, another entity may have
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* ownership of the resources, wait and try again to
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* see if they have relinquished the resources yet.
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@ -167,9 +167,9 @@ static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
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}
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/* Restart DSP and set SFI mode */
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IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
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IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL));
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IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((hw->mac.orig_autoc) |
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IXGBE_AUTOC_LMS_10G_SERIAL));
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hw->mac.cached_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
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ret_val = ixgbe_reset_pipeline_82599(hw);
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if (got_lock) {
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@ -803,12 +803,9 @@ static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
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bool autoneg_wait_to_complete)
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{
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s32 status = 0;
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u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
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u32 autoc, pma_pmd_1g, link_mode, start_autoc;
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u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
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u32 start_autoc = autoc;
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u32 orig_autoc = 0;
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u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
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u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
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u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
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u32 links_reg;
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u32 i;
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@ -831,9 +828,14 @@ static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
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/* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
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if (hw->mac.orig_link_settings_stored)
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orig_autoc = hw->mac.orig_autoc;
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autoc = hw->mac.orig_autoc;
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else
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orig_autoc = autoc;
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autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
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orig_autoc = autoc;
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start_autoc = hw->mac.cached_autoc;
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link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
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pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
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if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
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link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
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@ -887,6 +889,7 @@ static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
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/* Restart link */
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IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
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hw->mac.cached_autoc = autoc;
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ixgbe_reset_pipeline_82599(hw);
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if (got_lock)
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@ -958,7 +961,7 @@ static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
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{
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ixgbe_link_speed link_speed;
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s32 status;
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u32 ctrl, i, autoc, autoc2;
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u32 ctrl, i, autoc2;
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u32 curr_lms;
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bool link_up = false;
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@ -991,8 +994,12 @@ static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
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if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
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hw->phy.ops.reset(hw);
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/* remember AUTOC LMS from before we reset */
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curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK;
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/* remember AUTOC from before we reset */
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if (hw->mac.cached_autoc)
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curr_lms = hw->mac.cached_autoc & IXGBE_AUTOC_LMS_MASK;
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else
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curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) &
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IXGBE_AUTOC_LMS_MASK;
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mac_reset_top:
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/*
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@ -1042,10 +1049,18 @@ mac_reset_top:
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* stored off yet. Otherwise restore the stored original
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* values since the reset operation sets back to defaults.
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*/
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autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
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hw->mac.cached_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
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autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
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/* Enable link if disabled in NVM */
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if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
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autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
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IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
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IXGBE_WRITE_FLUSH(hw);
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}
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if (hw->mac.orig_link_settings_stored == false) {
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hw->mac.orig_autoc = autoc;
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hw->mac.orig_autoc = hw->mac.cached_autoc;
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hw->mac.orig_autoc2 = autoc2;
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hw->mac.orig_link_settings_stored = true;
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} else {
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@ -1062,7 +1077,7 @@ mac_reset_top:
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(hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
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curr_lms;
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if (autoc != hw->mac.orig_autoc) {
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if (hw->mac.cached_autoc != hw->mac.orig_autoc) {
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/* Need SW/FW semaphore around AUTOC writes if LESM is
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* on, likewise reset_pipeline requires us to hold
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* this lock as it also writes to AUTOC.
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@ -1078,6 +1093,7 @@ mac_reset_top:
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}
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IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
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hw->mac.cached_autoc = hw->mac.orig_autoc;
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ixgbe_reset_pipeline_82599(hw);
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if (got_lock)
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@ -2178,10 +2194,19 @@ static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
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**/
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s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
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{
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s32 i, autoc_reg, ret_val;
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s32 anlp1_reg = 0;
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s32 ret_val;
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u32 anlp1_reg = 0;
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u32 i, autoc_reg, autoc2_reg;
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autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
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/* Enable link if disabled in NVM */
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autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
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if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
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autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
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IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
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IXGBE_WRITE_FLUSH(hw);
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}
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autoc_reg = hw->mac.cached_autoc;
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autoc_reg |= IXGBE_AUTOC_AN_RESTART;
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/* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
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@ -440,7 +440,8 @@ static void ixgbe_get_regs(struct net_device *netdev,
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memset(p, 0, IXGBE_REGS_LEN * sizeof(u32));
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regs->version = (1 << 24) | hw->revision_id << 16 | hw->device_id;
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regs->version = hw->mac.type << 24 | hw->revision_id << 16 |
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hw->device_id;
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/* General Registers */
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regs_buff[0] = IXGBE_READ_REG(hw, IXGBE_CTRL);
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@ -1609,16 +1610,9 @@ static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
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struct ixgbe_hw *hw = &adapter->hw;
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u32 reg_data;
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/* X540 needs to set the MACC.FLU bit to force link up */
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if (adapter->hw.mac.type == ixgbe_mac_X540) {
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reg_data = IXGBE_READ_REG(hw, IXGBE_MACC);
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reg_data |= IXGBE_MACC_FLU;
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IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data);
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}
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/* right now we only support MAC loopback in the driver */
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reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0);
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/* Setup MAC loopback */
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reg_data = IXGBE_READ_REG(hw, IXGBE_HLREG0);
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reg_data |= IXGBE_HLREG0_LPBK;
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IXGBE_WRITE_REG(hw, IXGBE_HLREG0, reg_data);
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@ -1626,10 +1620,19 @@ static int ixgbe_setup_loopback_test(struct ixgbe_adapter *adapter)
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reg_data |= IXGBE_FCTRL_BAM | IXGBE_FCTRL_SBP | IXGBE_FCTRL_MPE;
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IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg_data);
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reg_data = IXGBE_READ_REG(hw, IXGBE_AUTOC);
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reg_data &= ~IXGBE_AUTOC_LMS_MASK;
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reg_data |= IXGBE_AUTOC_LMS_10G_LINK_NO_AN | IXGBE_AUTOC_FLU;
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IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data);
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/* X540 needs to set the MACC.FLU bit to force link up */
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if (adapter->hw.mac.type == ixgbe_mac_X540) {
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reg_data = IXGBE_READ_REG(hw, IXGBE_MACC);
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reg_data |= IXGBE_MACC_FLU;
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IXGBE_WRITE_REG(hw, IXGBE_MACC, reg_data);
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} else {
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if (hw->mac.orig_autoc) {
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reg_data = hw->mac.orig_autoc | IXGBE_AUTOC_FLU;
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IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_data);
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} else {
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return 10;
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}
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}
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IXGBE_WRITE_FLUSH(hw);
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usleep_range(10000, 20000);
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@ -2454,6 +2454,16 @@ static irqreturn_t ixgbe_msix_other(int irq, void *data)
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* with the write to EICR.
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*/
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eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
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/* The lower 16bits of the EICR register are for the queue interrupts
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* which should be masked here in order to not accidently clear them if
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* the bits are high when ixgbe_msix_other is called. There is a race
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* condition otherwise which results in possible performance loss
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* especially if the ixgbe_msix_other interrupt is triggering
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* consistently (as it would when PPS is turned on for the X540 device)
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*/
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eicr &= 0xFFFF0000;
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IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
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if (eicr & IXGBE_EICR_LSC)
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@ -1593,6 +1593,7 @@ enum {
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#define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
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#define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
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#define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
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#define IXGBE_AUTOC2_LINK_DISABLE_MASK 0x70000000
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#define IXGBE_MACC_FLU 0x00000001
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#define IXGBE_MACC_FSV_10G 0x00030000
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@ -2928,6 +2929,7 @@ struct ixgbe_mac_info {
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u32 max_tx_queues;
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u32 max_rx_queues;
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u32 orig_autoc;
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u32 cached_autoc;
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u32 orig_autoc2;
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bool orig_link_settings_stored;
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bool autotry_restart;
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