mt76: mt7921: use physical addr to unify register access
commit f1e2eef111 upstream.
Use physical address to unify the register access and reorder the
entries in fixed_map table to accelerate the address lookup for
MT7921e. Cosmetics the patch with adding an extra space to make all
entries in the array style consistent.
Tested-by: Deren Wu <deren.wu@mediatek.com>
Acked-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Sean Wang
Greg Kroah-Hartman
Родитель
191c16f921
Коммит
c3bcf1f959
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@ -125,36 +125,37 @@ static u32 __mt7921_reg_addr(struct mt7921_dev *dev, u32 addr)
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u32 mapped;
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u32 size;
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} fixed_map[] = {
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{ 0x00400000, 0x80000, 0x10000}, /* WF_MCU_SYSRAM */
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{ 0x00410000, 0x90000, 0x10000}, /* WF_MCU_SYSRAM (configure register) */
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{ 0x40000000, 0x70000, 0x10000}, /* WF_UMAC_SYSRAM */
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{ 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
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{ 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
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{ 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
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{ 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
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{ 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
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{ 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
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{ 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
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{ 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
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{ 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
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{ 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure register) */
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{ 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
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{ 0x54000000, 0x02000, 0x1000 }, /* WFDMA PCIE0 MCU DMA0 */
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{ 0x55000000, 0x03000, 0x1000 }, /* WFDMA PCIE0 MCU DMA1 */
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{ 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
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{ 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */
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{ 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
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{ 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
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{ 0x7c060000, 0xe0000, 0x10000}, /* CONN_INFRA, conn_host_csr_top */
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{ 0x7c060000, 0xe0000, 0x10000 }, /* CONN_INFRA, conn_host_csr_top */
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{ 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
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{ 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
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{ 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
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{ 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
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{ 0x820cc000, 0x0e000, 0x2000 }, /* WF_UMAC_TOP (PP) */
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{ 0x820cc000, 0x0e000, 0x1000 }, /* WF_UMAC_TOP (PP) */
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{ 0x820cd000, 0x0f000, 0x1000 }, /* WF_MDP_TOP */
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{ 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
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{ 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
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{ 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
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{ 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
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{ 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
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{ 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
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{ 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
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{ 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
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{ 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
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{ 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
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{ 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
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{ 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
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{ 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
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{ 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
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{ 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
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{ 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
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{ 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
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{ 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
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@ -14,7 +14,7 @@
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#define MT_MCU_INT_EVENT_SER_TRIGGER BIT(2)
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#define MT_MCU_INT_EVENT_RESET_DONE BIT(3)
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#define MT_PLE_BASE 0x8000
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#define MT_PLE_BASE 0x820c0000
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#define MT_PLE(ofs) (MT_PLE_BASE + (ofs))
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#define MT_PLE_FL_Q0_CTRL MT_PLE(0x3e0)
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@ -25,7 +25,7 @@
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#define MT_PLE_AC_QEMPTY(_n) MT_PLE(0x500 + 0x40 * (_n))
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#define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
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#define MT_MDP_BASE 0xf000
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#define MT_MDP_BASE 0x820cd000
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#define MT_MDP(ofs) (MT_MDP_BASE + (ofs))
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#define MT_MDP_DCR0 MT_MDP(0x000)
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@ -48,7 +48,7 @@
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#define MT_MDP_TO_WM 1
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/* TMAC: band 0(0x21000), band 1(0xa1000) */
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#define MT_WF_TMAC_BASE(_band) ((_band) ? 0xa1000 : 0x21000)
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#define MT_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000)
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#define MT_WF_TMAC(_band, ofs) (MT_WF_TMAC_BASE(_band) + (ofs))
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#define MT_TMAC_TCR0(_band) MT_WF_TMAC(_band, 0)
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@ -73,7 +73,7 @@
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#define MT_TMAC_TRCR0(_band) MT_WF_TMAC(_band, 0x09c)
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#define MT_TMAC_TFCR0(_band) MT_WF_TMAC(_band, 0x1e0)
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#define MT_WF_DMA_BASE(_band) ((_band) ? 0xa1e00 : 0x21e00)
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#define MT_WF_DMA_BASE(_band) ((_band) ? 0x820f7000 : 0x820e7000)
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#define MT_WF_DMA(_band, ofs) (MT_WF_DMA_BASE(_band) + (ofs))
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#define MT_DMA_DCR0(_band) MT_WF_DMA(_band, 0x000)
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@ -81,7 +81,7 @@
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#define MT_DMA_DCR0_RXD_G5_EN BIT(23)
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/* LPON: band 0(0x24200), band 1(0xa4200) */
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#define MT_WF_LPON_BASE(_band) ((_band) ? 0xa4200 : 0x24200)
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#define MT_WF_LPON_BASE(_band) ((_band) ? 0x820fb000 : 0x820eb000)
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#define MT_WF_LPON(_band, ofs) (MT_WF_LPON_BASE(_band) + (ofs))
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#define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, 0x080)
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@ -92,7 +92,7 @@
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#define MT_LPON_TCR_SW_WRITE BIT(0)
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/* MIB: band 0(0x24800), band 1(0xa4800) */
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#define MT_WF_MIB_BASE(_band) ((_band) ? 0xa4800 : 0x24800)
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#define MT_WF_MIB_BASE(_band) ((_band) ? 0x820fd000 : 0x820ed000)
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#define MT_WF_MIB(_band, ofs) (MT_WF_MIB_BASE(_band) + (ofs))
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#define MT_MIB_SCR1(_band) MT_WF_MIB(_band, 0x004)
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@ -141,7 +141,7 @@
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#define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, 0x0b0 + ((n) << 2))
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#define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(7, 0))
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#define MT_WTBLON_TOP_BASE 0x34000
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#define MT_WTBLON_TOP_BASE 0x820d4000
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#define MT_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs))
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#define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(0x200)
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#define MT_WTBLON_TOP_WDUCR_GROUP GENMASK(2, 0)
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@ -151,7 +151,7 @@
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#define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12)
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#define MT_WTBL_UPDATE_BUSY BIT(31)
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#define MT_WTBL_BASE 0x38000
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#define MT_WTBL_BASE 0x820d8000
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#define MT_WTBL_LMAC_ID GENMASK(14, 8)
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#define MT_WTBL_LMAC_DW GENMASK(7, 2)
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#define MT_WTBL_LMAC_OFFS(_id, _dw) (MT_WTBL_BASE | \
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@ -159,7 +159,7 @@
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FIELD_PREP(MT_WTBL_LMAC_DW, _dw))
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/* AGG: band 0(0x20800), band 1(0xa0800) */
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#define MT_WF_AGG_BASE(_band) ((_band) ? 0xa0800 : 0x20800)
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#define MT_WF_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000)
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#define MT_WF_AGG(_band, ofs) (MT_WF_AGG_BASE(_band) + (ofs))
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#define MT_AGG_AWSCR0(_band, _n) MT_WF_AGG(_band, 0x05c + (_n) * 4)
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@ -190,7 +190,7 @@
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#define MT_AGG_ATCR3(_band) MT_WF_AGG(_band, 0x0f4)
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/* ARB: band 0(0x20c00), band 1(0xa0c00) */
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#define MT_WF_ARB_BASE(_band) ((_band) ? 0xa0c00 : 0x20c00)
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#define MT_WF_ARB_BASE(_band) ((_band) ? 0x820f3000 : 0x820e3000)
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#define MT_WF_ARB(_band, ofs) (MT_WF_ARB_BASE(_band) + (ofs))
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#define MT_ARB_SCR(_band) MT_WF_ARB(_band, 0x080)
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@ -200,7 +200,7 @@
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#define MT_ARB_DRNGR0(_band, _n) MT_WF_ARB(_band, 0x194 + (_n) * 4)
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/* RMAC: band 0(0x21400), band 1(0xa1400) */
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#define MT_WF_RMAC_BASE(_band) ((_band) ? 0xa1400 : 0x21400)
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#define MT_WF_RMAC_BASE(_band) ((_band) ? 0x820f5000 : 0x820e5000)
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#define MT_WF_RMAC(_band, ofs) (MT_WF_RMAC_BASE(_band) + (ofs))
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#define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000)
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