mxser: cleanup mxser_process_txrx_fifo
Rename process_txrx_fifo to mxser_process_txrx_fifo and: * remove useless parentheses * return from the 'if's true branch and process the rest in normal code flow (shift the code one level left) All this to make the code more readable. Signed-off-by: Jiri Slaby <jslaby@suse.cz> Link: https://lore.kernel.org/r/20210618061516.662-50-jslaby@suse.cz Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Родитель
c24c31ff4a
Коммит
c3db20c3b7
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@ -398,22 +398,24 @@ static enum mxser_must_hwid mxser_must_get_hwid(unsigned long io)
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return MOXA_OTHER_UART;
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return MOXA_OTHER_UART;
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}
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}
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static void process_txrx_fifo(struct mxser_port *info)
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static void mxser_process_txrx_fifo(struct mxser_port *info)
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{
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{
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int i;
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unsigned int i;
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if ((info->type == PORT_16450) || (info->type == PORT_8250)) {
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if (info->type == PORT_16450 || info->type == PORT_8250) {
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info->rx_high_water = 1;
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info->rx_high_water = 1;
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info->rx_low_water = 1;
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info->rx_low_water = 1;
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info->xmit_fifo_size = 1;
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info->xmit_fifo_size = 1;
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} else
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return;
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for (i = 0; i < UART_INFO_NUM; i++)
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}
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if (info->board->must_hwid == Gpci_uart_info[i].type) {
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info->rx_low_water = Gpci_uart_info[i].rx_low_water;
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for (i = 0; i < UART_INFO_NUM; i++)
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info->rx_high_water = Gpci_uart_info[i].rx_high_water;
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if (info->board->must_hwid == Gpci_uart_info[i].type) {
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info->xmit_fifo_size = Gpci_uart_info[i].fifo_size;
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info->rx_low_water = Gpci_uart_info[i].rx_low_water;
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break;
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info->rx_high_water = Gpci_uart_info[i].rx_high_water;
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}
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info->xmit_fifo_size = Gpci_uart_info[i].fifo_size;
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break;
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}
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}
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}
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static int mxser_carrier_raised(struct tty_port *port)
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static int mxser_carrier_raised(struct tty_port *port)
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@ -1149,7 +1151,7 @@ static int mxser_set_serial_info(struct tty_struct *tty,
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info->type = ss->type;
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info->type = ss->type;
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process_txrx_fifo(info);
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mxser_process_txrx_fifo(info);
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}
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}
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if (tty_port_initialized(port)) {
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if (tty_port_initialized(port)) {
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@ -1895,7 +1897,7 @@ static void mxser_initbrd(struct mxser_board *brd, bool high_baud)
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info->type = PORT_16550A;
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info->type = PORT_16550A;
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process_txrx_fifo(info);
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mxser_process_txrx_fifo(info);
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info->port.close_delay = 5 * HZ / 10;
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info->port.close_delay = 5 * HZ / 10;
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info->port.closing_wait = 30 * HZ;
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info->port.closing_wait = 30 * HZ;
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