[PATCH] hwmon: Add PEC support to the lm90 driver
Add PEC support to the lm90 driver. Only the ADM1032 chip supports it, and in a rather tricky way, which is why this patch comes with documentation reinforcements. At least, this demonstrates that the new PEC support logic in i2c-core can properly deal with chips with partial PEC support. As enabling PEC causes a significant performance drop, it can be disabled through a sysfs file (unsurprisingly named "pec"). Signed-off-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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@ -71,8 +71,8 @@ increased resolution of the remote temperature measurement.
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The different chipsets of the family are not strictly identical, although
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very similar. This driver doesn't handle any specific feature for now,
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but could if there ever was a need for it. For reference, here comes a
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non-exhaustive list of specific features:
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with the exception of SMBus PEC. For reference, here comes a non-exhaustive
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list of specific features:
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LM90:
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* Filter and alert configuration register at 0xBF.
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@ -91,6 +91,7 @@ ADM1032:
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* Conversion averaging.
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* Up to 64 conversions/s.
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* ALERT is triggered by open remote sensor.
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* SMBus PEC support for Write Byte and Receive Byte transactions.
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ADT7461
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* Extended temperature range (breaks compatibility)
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@ -119,3 +120,37 @@ The lm90 driver will not update its values more frequently than every
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other second; reading them more often will do no harm, but will return
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'old' values.
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PEC Support
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-----------
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The ADM1032 is the only chip of the family which supports PEC. It does
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not support PEC on all transactions though, so some care must be taken.
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When reading a register value, the PEC byte is computed and sent by the
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ADM1032 chip. However, in the case of a combined transaction (SMBus Read
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Byte), the ADM1032 computes the CRC value over only the second half of
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the message rather than its entirety, because it thinks the first half
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of the message belongs to a different transaction. As a result, the CRC
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value differs from what the SMBus master expects, and all reads fail.
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For this reason, the lm90 driver will enable PEC for the ADM1032 only if
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the bus supports the SMBus Send Byte and Receive Byte transaction types.
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These transactions will be used to read register values, instead of
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SMBus Read Byte, and PEC will work properly.
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Additionally, the ADM1032 doesn't support SMBus Send Byte with PEC.
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Instead, it will try to write the PEC value to the register (because the
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SMBus Send Byte transaction with PEC is similar to a Write Byte transaction
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without PEC), which is not what we want. Thus, PEC is explicitely disabled
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on SMBus Send Byte transactions in the lm90 driver.
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PEC on byte data transactions represents a significant increase in bandwidth
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usage (+33% for writes, +25% for reads) in normal conditions. With the need
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to use two SMBus transaction for reads, this overhead jumps to +50%. Worse,
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two transactions will typically mean twice as much delay waiting for
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transaction completion, effectively doubling the register cache refresh time.
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I guess reliability comes at a price, but it's quite expensive this time.
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So, as not everyone might enjoy the slowdown, PEC can be disabled through
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sysfs. Just write 0 to the "pec" file and PEC will be disabled. Write 1
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to that file to enable PEC again.
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@ -272,3 +272,6 @@ beep_mask Bitmask for beep.
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eeprom Raw EEPROM data in binary form.
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Read only.
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pec Enable or disable PEC (SMBus only)
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Read/Write
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@ -345,15 +345,63 @@ static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IWUSR | S_IRUGO, show_temphyst,
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static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, show_temphyst, NULL, 4);
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static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
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/* pec used for ADM1032 only */
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static ssize_t show_pec(struct device *dev, struct device_attribute *dummy,
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char *buf)
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{
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struct i2c_client *client = to_i2c_client(dev);
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return sprintf(buf, "%d\n", !!(client->flags & I2C_CLIENT_PEC));
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}
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static ssize_t set_pec(struct device *dev, struct device_attribute *dummy,
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const char *buf, size_t count)
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{
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struct i2c_client *client = to_i2c_client(dev);
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long val = simple_strtol(buf, NULL, 10);
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switch (val) {
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case 0:
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client->flags &= ~I2C_CLIENT_PEC;
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break;
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case 1:
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client->flags |= I2C_CLIENT_PEC;
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break;
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default:
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return -EINVAL;
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}
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return count;
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}
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static DEVICE_ATTR(pec, S_IWUSR | S_IRUGO, show_pec, set_pec);
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/*
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* Real code
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*/
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/* The ADM1032 supports PEC but not on write byte transactions, so we need
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to explicitely ask for a transaction without PEC. */
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static inline s32 adm1032_write_byte(struct i2c_client *client, u8 value)
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{
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return i2c_smbus_xfer(client->adapter, client->addr,
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client->flags & ~I2C_CLIENT_PEC,
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I2C_SMBUS_WRITE, value, I2C_SMBUS_BYTE, NULL);
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}
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/* It is assumed that client->update_lock is held (unless we are in
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detection or initialization steps). This matters when PEC is enabled,
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because we don't want the address pointer to change between the write
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byte and the read byte transactions. */
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static int lm90_read_reg(struct i2c_client* client, u8 reg, u8 *value)
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{
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int err;
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err = i2c_smbus_read_byte_data(client, reg);
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if (client->flags & I2C_CLIENT_PEC) {
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err = adm1032_write_byte(client, reg);
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if (err >= 0)
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err = i2c_smbus_read_byte(client);
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} else
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err = i2c_smbus_read_byte_data(client, reg);
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if (err < 0) {
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dev_warn(&client->dev, "Register %#02x read failed (%d)\n",
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@ -494,6 +542,10 @@ static int lm90_detect(struct i2c_adapter *adapter, int address, int kind)
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name = "lm90";
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} else if (kind == adm1032) {
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name = "adm1032";
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/* The ADM1032 supports PEC, but only if combined
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transactions are not used. */
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if (i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE))
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new_client->flags |= I2C_CLIENT_PEC;
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} else if (kind == lm99) {
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name = "lm99";
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} else if (kind == lm86) {
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@ -546,6 +598,9 @@ static int lm90_detect(struct i2c_adapter *adapter, int address, int kind)
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&sensor_dev_attr_temp2_crit_hyst.dev_attr);
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device_create_file(&new_client->dev, &dev_attr_alarms);
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if (new_client->flags & I2C_CLIENT_PEC)
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device_create_file(&new_client->dev, &dev_attr_pec);
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return 0;
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exit_detach:
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