[AGPGART] fix detection of aperture size versus GTT size on G965
On the G965, the GTT size may be larger than is required to cover the aperture. (In fact, on all hardware we've seen, the GTT is 512KB to the aperture's 256MB). A previous commit forced the aperture size to 512MB on G965 to match GTT, which would likely result in hangs at best if users tried to rely on agpgart's aperture size information. Instead, we use the resource length for the aperture size and the system's reported GTT size when available for the GTT size. Because the MSAC registers which had been read for aperture size detection on i9xx chips just cause a change in the resource size, we can use generic code for aperture detection on all i9xx. Signed-off-by: Eric Anholt <eric@anholt.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Dave Jones <davej@redhat.com>
This commit is contained in:
Eric Anholt
Dave Jones
Родитель
5aa80c7226
Коммит
c41e0deb50
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@ -225,6 +225,10 @@ struct agp_bridge_data {
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#define I810_GMS_DISABLE 0x00000000
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#define I810_PGETBL_CTL 0x2020
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#define I810_PGETBL_ENABLED 0x00000001
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#define I965_PGETBL_SIZE_MASK 0x0000000e
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#define I965_PGETBL_SIZE_512KB (0 << 1)
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#define I965_PGETBL_SIZE_256KB (1 << 1)
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#define I965_PGETBL_SIZE_128KB (2 << 1)
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#define I810_DRAM_CTL 0x3000
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#define I810_DRAM_ROW_0 0x00000001
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#define I810_DRAM_ROW_0_SDRAM 0x00000001
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@ -382,6 +382,11 @@ static struct _intel_i830_private {
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struct pci_dev *i830_dev; /* device one */
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volatile u8 __iomem *registers;
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volatile u32 __iomem *gtt; /* I915G */
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/* gtt_entries is the number of gtt entries that are already mapped
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* to stolen memory. Stolen memory is larger than the memory mapped
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* through gtt_entries, as it includes some reserved space for the BIOS
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* popup and for the GTT.
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*/
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int gtt_entries;
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} intel_i830_private;
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@ -392,14 +397,41 @@ static void intel_i830_init_gtt_entries(void)
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u8 rdct;
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int local = 0;
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static const int ddt[4] = { 0, 16, 32, 64 };
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int size;
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int size; /* reserved space (in kb) at the top of stolen memory */
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pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
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/* We obtain the size of the GTT, which is also stored (for some
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* reason) at the top of stolen memory. Then we add 4KB to that
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* for the video BIOS popup, which is also stored in there. */
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size = agp_bridge->driver->fetch_size() + 4;
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if (IS_I965) {
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u32 pgetbl_ctl;
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pci_read_config_dword(agp_bridge->dev, I810_PGETBL_CTL,
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&pgetbl_ctl);
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/* The 965 has a field telling us the size of the GTT,
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* which may be larger than what is necessary to map the
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* aperture.
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*/
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switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
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case I965_PGETBL_SIZE_128KB:
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size = 128;
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break;
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case I965_PGETBL_SIZE_256KB:
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size = 256;
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break;
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case I965_PGETBL_SIZE_512KB:
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size = 512;
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break;
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default:
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printk(KERN_INFO PFX "Unknown page table size, "
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"assuming 512KB\n");
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size = 512;
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}
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size += 4; /* add in BIOS popup space */
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} else {
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/* On previous hardware, the GTT size was just what was
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* required to map the aperture.
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*/
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size = agp_bridge->driver->fetch_size() + 4;
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}
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if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
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agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
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@ -765,22 +797,27 @@ static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start,
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return 0;
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}
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static int intel_i915_fetch_size(void)
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/* Return the aperture size by just checking the resource length. The effect
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* described in the spec of the MSAC registers is just changing of the
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* resource size.
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*/
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static int intel_i9xx_fetch_size(void)
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{
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struct aper_size_info_fixed *values;
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u32 temp, offset;
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int num_sizes = sizeof(intel_i830_sizes) / sizeof(*intel_i830_sizes);
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int aper_size; /* size in megabytes */
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int i;
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#define I915_256MB_ADDRESS_MASK (1<<27)
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aper_size = pci_resource_len(intel_i830_private.i830_dev, 2) / MB(1);
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values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
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for (i = 0; i < num_sizes; i++) {
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if (aper_size == intel_i830_sizes[i].size) {
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agp_bridge->current_size = intel_i830_sizes + i;
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agp_bridge->previous_size = agp_bridge->current_size;
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return aper_size;
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}
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}
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pci_read_config_dword(intel_i830_private.i830_dev, I915_GMADDR, &temp);
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if (temp & I915_256MB_ADDRESS_MASK)
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offset = 0; /* 128MB aperture */
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else
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offset = 2; /* 256MB aperture */
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agp_bridge->previous_size = agp_bridge->current_size = (void *)(values + offset);
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return values[offset].size;
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return 0;
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}
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/* The intel i915 automatically initializes the agp aperture during POST.
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@ -843,40 +880,9 @@ static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
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return addr | bridge->driver->masks[type].mask;
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}
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static int intel_i965_fetch_size(void)
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{
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struct aper_size_info_fixed *values;
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u32 offset = 0;
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u8 temp;
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#define I965_512MB_ADDRESS_MASK (3<<1)
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values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
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pci_read_config_byte(intel_i830_private.i830_dev, I965_MSAC, &temp);
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temp &= I965_512MB_ADDRESS_MASK;
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switch (temp) {
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case 0x00:
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offset = 0; /* 128MB */
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break;
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case 0x06:
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offset = 3; /* 512MB */
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break;
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default:
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case 0x02:
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offset = 2; /* 256MB */
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break;
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}
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agp_bridge->previous_size = agp_bridge->current_size = (void *)(values + offset);
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/* The i965 GTT is always sized as if it had a 512kB aperture size */
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return 512;
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}
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/* The intel i965 automatically initializes the agp aperture during POST.
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+ * Use the memory already set aside for in the GTT.
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+ */
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* Use the memory already set aside for in the GTT.
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*/
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static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
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{
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int page_order;
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@ -1596,7 +1602,7 @@ static struct agp_bridge_driver intel_915_driver = {
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.num_aperture_sizes = 4,
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.needs_scratch_page = TRUE,
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.configure = intel_i915_configure,
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.fetch_size = intel_i915_fetch_size,
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.fetch_size = intel_i9xx_fetch_size,
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.cleanup = intel_i915_cleanup,
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.tlb_flush = intel_i810_tlbflush,
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.mask_memory = intel_i810_mask_memory,
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@ -1620,7 +1626,7 @@ static struct agp_bridge_driver intel_i965_driver = {
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.num_aperture_sizes = 4,
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.needs_scratch_page = TRUE,
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.configure = intel_i915_configure,
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.fetch_size = intel_i965_fetch_size,
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.fetch_size = intel_i9xx_fetch_size,
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.cleanup = intel_i915_cleanup,
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.tlb_flush = intel_i810_tlbflush,
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.mask_memory = intel_i965_mask_memory,
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