mfd: stmpe: Add reset support for all STMPE variant
Reset was only implemented for STMPE1801 variant despite all variant have a SOFT_RESET bit. For STMPE2401/2403/801/1601/1801 SOFT_RESET bit is bit 7 of SYS_CTRL register. For STMPE610/811 (which have the same variant id) SOFT_RESET bit is bit 1 of SYS_CTRL register. Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>
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Родитель
0f4be8cf63
Коммит
c4dd1ba355
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@ -756,13 +756,22 @@ static int stmpe1801_enable(struct stmpe *stmpe, unsigned int blocks,
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enable ? mask : 0);
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enable ? mask : 0);
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}
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}
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static int stmpe1801_reset(struct stmpe *stmpe)
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static int stmpe_reset(struct stmpe *stmpe)
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{
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{
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u16 id_val = stmpe->variant->id_val;
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unsigned long timeout;
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unsigned long timeout;
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int ret = 0;
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int ret = 0;
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u8 reset_bit;
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if (id_val == STMPE811_ID)
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/* STMPE801 and STMPE610 use bit 1 of SYS_CTRL register */
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reset_bit = STMPE811_SYS_CTRL_RESET;
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else
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/* all other STMPE variant use bit 7 of SYS_CTRL register */
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reset_bit = STMPE_SYS_CTRL_RESET;
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ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL],
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ret = __stmpe_set_bits(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL],
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STMPE1801_MSK_SYS_CTRL_RESET, STMPE1801_MSK_SYS_CTRL_RESET);
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reset_bit, reset_bit);
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if (ret < 0)
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if (ret < 0)
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return ret;
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return ret;
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@ -771,7 +780,7 @@ static int stmpe1801_reset(struct stmpe *stmpe)
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ret = __stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL]);
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ret = __stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_SYS_CTRL]);
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if (ret < 0)
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if (ret < 0)
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return ret;
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return ret;
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if (!(ret & STMPE1801_MSK_SYS_CTRL_RESET))
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if (!(ret & reset_bit))
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return 0;
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return 0;
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usleep_range(100, 200);
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usleep_range(100, 200);
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}
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}
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@ -1095,11 +1104,9 @@ static int stmpe_chip_init(struct stmpe *stmpe)
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if (ret)
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if (ret)
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return ret;
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return ret;
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if (id == STMPE1801_ID) {
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ret = stmpe_reset(stmpe);
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ret = stmpe1801_reset(stmpe);
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if (ret < 0)
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if (ret < 0)
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return ret;
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return ret;
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}
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if (stmpe->irq >= 0) {
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if (stmpe->irq >= 0) {
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if (id == STMPE801_ID)
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if (id == STMPE801_ID)
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@ -104,6 +104,8 @@ int stmpe_remove(struct stmpe *stmpe);
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#define STMPE_ICR_LSB_EDGE (1 << 1)
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#define STMPE_ICR_LSB_EDGE (1 << 1)
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#define STMPE_ICR_LSB_GIM (1 << 0)
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#define STMPE_ICR_LSB_GIM (1 << 0)
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#define STMPE_SYS_CTRL_RESET (1 << 7)
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/*
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/*
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* STMPE801
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* STMPE801
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*/
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*/
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@ -126,6 +128,7 @@ int stmpe_remove(struct stmpe *stmpe);
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/*
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/*
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* STMPE811
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* STMPE811
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*/
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*/
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#define STMPE811_ID 0x0811
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#define STMPE811_IRQ_TOUCH_DET 0
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#define STMPE811_IRQ_TOUCH_DET 0
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#define STMPE811_IRQ_FIFO_TH 1
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#define STMPE811_IRQ_FIFO_TH 1
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@ -155,6 +158,8 @@ int stmpe_remove(struct stmpe *stmpe);
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#define STMPE811_REG_GPIO_FE 0x16
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#define STMPE811_REG_GPIO_FE 0x16
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#define STMPE811_REG_GPIO_AF 0x17
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#define STMPE811_REG_GPIO_AF 0x17
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#define STMPE811_SYS_CTRL_RESET (1 << 1)
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#define STMPE811_SYS_CTRL2_ADC_OFF (1 << 0)
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#define STMPE811_SYS_CTRL2_ADC_OFF (1 << 0)
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#define STMPE811_SYS_CTRL2_TSC_OFF (1 << 1)
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#define STMPE811_SYS_CTRL2_TSC_OFF (1 << 1)
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#define STMPE811_SYS_CTRL2_GPIO_OFF (1 << 2)
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#define STMPE811_SYS_CTRL2_GPIO_OFF (1 << 2)
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@ -244,8 +249,6 @@ int stmpe_remove(struct stmpe *stmpe);
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#define STMPE1801_REG_GPIO_PULL_UP_MID 0x23
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#define STMPE1801_REG_GPIO_PULL_UP_MID 0x23
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#define STMPE1801_REG_GPIO_PULL_UP_HIGH 0x24
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#define STMPE1801_REG_GPIO_PULL_UP_HIGH 0x24
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#define STMPE1801_MSK_SYS_CTRL_RESET (1 << 7)
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#define STMPE1801_MSK_INT_EN_KPC (1 << 1)
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#define STMPE1801_MSK_INT_EN_KPC (1 << 1)
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#define STMPE1801_MSK_INT_EN_GPIO (1 << 3)
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#define STMPE1801_MSK_INT_EN_GPIO (1 << 3)
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