Merge remote-tracking branches 'spi/topic/res', 'spi/topic/rockchip', 'spi/topic/sh', 'spi/topic/ti-qspi' and 'spi/topic/xilinx' into spi-next
This commit is contained in:
Mark Brown
Коммит
c508709bcf
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@ -9,6 +9,7 @@ Required Properties:
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"rockchip,rk3066-spi" for rk3066.
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"rockchip,rk3188-spi", "rockchip,rk3066-spi" for rk3188.
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"rockchip,rk3288-spi", "rockchip,rk3066-spi" for rk3288.
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"rockchip,rk3399-spi", "rockchip,rk3066-spi" for rk3399.
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- reg: physical base address of the controller and length of memory mapped
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region.
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- interrupts: The interrupt number to the cpu. The interrupt specifier format
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@ -0,0 +1,22 @@
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Xilinx SPI controller Device Tree Bindings
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-------------------------------------------------
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Required properties:
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- compatible : Should be "xlnx,xps-spi-2.00.a" or "xlnx,xps-spi-2.00.b"
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- reg : Physical base address and size of SPI registers map.
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- interrupts : Property with a value describing the interrupt
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number.
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- interrupt-parent : Must be core interrupt controller
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Optional properties:
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- xlnx,num-ss-bits : Number of chip selects used.
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Example:
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axi_quad_spi@41e00000 {
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compatible = "xlnx,xps-spi-2.00.a";
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interrupt-parent = <&intc>;
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interrupts = <0 31 1>;
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reg = <0x41e00000 0x10000>;
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xlnx,num-ss-bits = <0x1>;
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};
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@ -487,7 +487,7 @@ config SPI_RB4XX
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config SPI_RSPI
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tristate "Renesas RSPI/QSPI controller"
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depends on SUPERH || ARCH_SHMOBILE || COMPILE_TEST
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depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
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help
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SPI driver for Renesas RSPI and QSPI blocks.
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@ -537,7 +537,7 @@ config SPI_SC18IS602
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config SPI_SH_MSIOF
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tristate "SuperH MSIOF SPI controller"
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depends on HAVE_CLK && HAS_DMA
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depends on SUPERH || ARCH_SHMOBILE || COMPILE_TEST
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depends on SUPERH || ARCH_RENESAS || COMPILE_TEST
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help
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SPI driver for SuperH and SH Mobile MSIOF blocks.
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@ -556,7 +556,7 @@ config SPI_SH_SCI
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config SPI_SH_HSPI
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tristate "SuperH HSPI controller"
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depends on ARCH_SHMOBILE || COMPILE_TEST
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depends on ARCH_RENESAS || COMPILE_TEST
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help
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SPI driver for SuperH HSPI blocks.
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@ -13,20 +13,14 @@
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spi/spi.h>
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#include <linux/scatterlist.h>
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#include <linux/of.h>
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#include <linux/pm_runtime.h>
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#include <linux/io.h>
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#include <linux/dmaengine.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/spi/spi.h>
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#include <linux/pm_runtime.h>
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#include <linux/scatterlist.h>
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#define DRIVER_NAME "rockchip-spi"
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@ -179,7 +173,7 @@ struct rockchip_spi {
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u8 tmode;
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u8 bpw;
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u8 n_bytes;
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u8 rsd_nsecs;
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u32 rsd_nsecs;
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unsigned len;
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u32 speed;
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@ -192,8 +186,6 @@ struct rockchip_spi {
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/* protect state */
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spinlock_t lock;
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struct completion xfer_completion;
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u32 use_dma;
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struct sg_table tx_sg;
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struct sg_table rx_sg;
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@ -265,7 +257,10 @@ static inline u32 rx_max(struct rockchip_spi *rs)
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static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
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{
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u32 ser;
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struct rockchip_spi *rs = spi_master_get_devdata(spi->master);
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struct spi_master *master = spi->master;
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struct rockchip_spi *rs = spi_master_get_devdata(master);
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pm_runtime_get_sync(rs->dev);
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ser = readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & SER_MASK;
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@ -290,6 +285,8 @@ static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
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ser &= ~(1 << spi->chip_select);
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writel_relaxed(ser, rs->regs + ROCKCHIP_SPI_SER);
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pm_runtime_put_sync(rs->dev);
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}
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static int rockchip_spi_prepare_message(struct spi_master *master,
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@ -319,12 +316,12 @@ static void rockchip_spi_handle_err(struct spi_master *master,
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*/
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if (rs->use_dma) {
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if (rs->state & RXBUSY) {
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dmaengine_terminate_all(rs->dma_rx.ch);
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dmaengine_terminate_async(rs->dma_rx.ch);
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flush_fifo(rs);
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}
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if (rs->state & TXBUSY)
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dmaengine_terminate_all(rs->dma_tx.ch);
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dmaengine_terminate_async(rs->dma_tx.ch);
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}
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spin_unlock_irqrestore(&rs->lock, flags);
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@ -433,7 +430,7 @@ static void rockchip_spi_dma_txcb(void *data)
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spin_unlock_irqrestore(&rs->lock, flags);
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}
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static void rockchip_spi_prepare_dma(struct rockchip_spi *rs)
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static int rockchip_spi_prepare_dma(struct rockchip_spi *rs)
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{
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unsigned long flags;
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struct dma_slave_config rxconf, txconf;
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@ -456,6 +453,8 @@ static void rockchip_spi_prepare_dma(struct rockchip_spi *rs)
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rs->dma_rx.ch,
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rs->rx_sg.sgl, rs->rx_sg.nents,
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rs->dma_rx.direction, DMA_PREP_INTERRUPT);
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if (!rxdesc)
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return -EINVAL;
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rxdesc->callback = rockchip_spi_dma_rxcb;
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rxdesc->callback_param = rs;
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@ -473,6 +472,11 @@ static void rockchip_spi_prepare_dma(struct rockchip_spi *rs)
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rs->dma_tx.ch,
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rs->tx_sg.sgl, rs->tx_sg.nents,
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rs->dma_tx.direction, DMA_PREP_INTERRUPT);
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if (!txdesc) {
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if (rxdesc)
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dmaengine_terminate_sync(rs->dma_rx.ch);
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return -EINVAL;
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}
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txdesc->callback = rockchip_spi_dma_txcb;
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txdesc->callback_param = rs;
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@ -494,6 +498,8 @@ static void rockchip_spi_prepare_dma(struct rockchip_spi *rs)
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dmaengine_submit(txdesc);
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dma_async_issue_pending(rs->dma_tx.ch);
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}
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return 0;
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}
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static void rockchip_spi_config(struct rockchip_spi *rs)
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@ -503,7 +509,8 @@ static void rockchip_spi_config(struct rockchip_spi *rs)
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int rsd = 0;
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u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET)
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| (CR0_SSD_ONE << CR0_SSD_OFFSET);
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| (CR0_SSD_ONE << CR0_SSD_OFFSET)
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| (CR0_EM_BIG << CR0_EM_OFFSET);
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cr0 |= (rs->n_bytes << CR0_DFS_OFFSET);
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cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET);
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@ -606,12 +613,12 @@ static int rockchip_spi_transfer_one(
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if (rs->use_dma) {
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if (rs->tmode == CR0_XFM_RO) {
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/* rx: dma must be prepared first */
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rockchip_spi_prepare_dma(rs);
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ret = rockchip_spi_prepare_dma(rs);
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spi_enable_chip(rs, 1);
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} else {
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/* tx or tr: spi must be enabled first */
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spi_enable_chip(rs, 1);
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rockchip_spi_prepare_dma(rs);
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ret = rockchip_spi_prepare_dma(rs);
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}
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} else {
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spi_enable_chip(rs, 1);
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@ -717,8 +724,14 @@ static int rockchip_spi_probe(struct platform_device *pdev)
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master->handle_err = rockchip_spi_handle_err;
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rs->dma_tx.ch = dma_request_slave_channel(rs->dev, "tx");
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if (!rs->dma_tx.ch)
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if (IS_ERR_OR_NULL(rs->dma_tx.ch)) {
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/* Check tx to see if we need defer probing driver */
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if (PTR_ERR(rs->dma_tx.ch) == -EPROBE_DEFER) {
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ret = -EPROBE_DEFER;
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goto err_get_fifo_len;
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}
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dev_warn(rs->dev, "Failed to request TX DMA channel\n");
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}
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rs->dma_rx.ch = dma_request_slave_channel(rs->dev, "rx");
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if (!rs->dma_rx.ch) {
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@ -871,6 +884,7 @@ static const struct of_device_id rockchip_spi_dt_match[] = {
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{ .compatible = "rockchip,rk3066-spi", },
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{ .compatible = "rockchip,rk3188-spi", },
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{ .compatible = "rockchip,rk3288-spi", },
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{ .compatible = "rockchip,rk3399-spi", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
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@ -31,6 +31,8 @@
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include <linux/spi/spi.h>
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@ -44,8 +46,9 @@ struct ti_qspi {
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struct spi_master *master;
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void __iomem *base;
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void __iomem *ctrl_base;
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void __iomem *mmap_base;
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struct regmap *ctrl_base;
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unsigned int ctrl_reg;
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struct clk *fclk;
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struct device *dev;
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@ -55,7 +58,7 @@ struct ti_qspi {
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u32 cmd;
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u32 dc;
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bool ctrl_mod;
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bool mmap_enabled;
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};
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#define QSPI_PID (0x0)
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@ -65,11 +68,8 @@ struct ti_qspi {
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#define QSPI_SPI_CMD_REG (0x48)
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#define QSPI_SPI_STATUS_REG (0x4c)
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#define QSPI_SPI_DATA_REG (0x50)
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#define QSPI_SPI_SETUP0_REG (0x54)
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#define QSPI_SPI_SETUP_REG(n) ((0x54 + 4 * n))
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#define QSPI_SPI_SWITCH_REG (0x64)
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#define QSPI_SPI_SETUP1_REG (0x58)
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#define QSPI_SPI_SETUP2_REG (0x5c)
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#define QSPI_SPI_SETUP3_REG (0x60)
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#define QSPI_SPI_DATA_REG_1 (0x68)
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#define QSPI_SPI_DATA_REG_2 (0x6c)
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#define QSPI_SPI_DATA_REG_3 (0x70)
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@ -109,6 +109,17 @@ struct ti_qspi {
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|
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#define QSPI_AUTOSUSPEND_TIMEOUT 2000
|
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|
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#define MEM_CS_EN(n) ((n + 1) << 8)
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#define MEM_CS_MASK (7 << 8)
|
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|
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#define MM_SWITCH 0x1
|
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|
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#define QSPI_SETUP_RD_NORMAL (0x0 << 12)
|
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#define QSPI_SETUP_RD_DUAL (0x1 << 12)
|
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#define QSPI_SETUP_RD_QUAD (0x3 << 12)
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#define QSPI_SETUP_ADDR_SHIFT 8
|
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#define QSPI_SETUP_DUMMY_SHIFT 10
|
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|
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static inline unsigned long ti_qspi_read(struct ti_qspi *qspi,
|
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unsigned long reg)
|
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{
|
||||
|
|
@ -366,6 +377,72 @@ static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t)
|
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return 0;
|
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}
|
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|
||||
static void ti_qspi_enable_memory_map(struct spi_device *spi)
|
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{
|
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struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
|
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|
||||
ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG);
|
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if (qspi->ctrl_base) {
|
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regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
|
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MEM_CS_EN(spi->chip_select),
|
||||
MEM_CS_MASK);
|
||||
}
|
||||
qspi->mmap_enabled = true;
|
||||
}
|
||||
|
||||
static void ti_qspi_disable_memory_map(struct spi_device *spi)
|
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{
|
||||
struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
|
||||
|
||||
ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG);
|
||||
if (qspi->ctrl_base)
|
||||
regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg,
|
||||
0, MEM_CS_MASK);
|
||||
qspi->mmap_enabled = false;
|
||||
}
|
||||
|
||||
static void ti_qspi_setup_mmap_read(struct spi_device *spi,
|
||||
struct spi_flash_read_message *msg)
|
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{
|
||||
struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
|
||||
u32 memval = msg->read_opcode;
|
||||
|
||||
switch (msg->data_nbits) {
|
||||
case SPI_NBITS_QUAD:
|
||||
memval |= QSPI_SETUP_RD_QUAD;
|
||||
break;
|
||||
case SPI_NBITS_DUAL:
|
||||
memval |= QSPI_SETUP_RD_DUAL;
|
||||
break;
|
||||
default:
|
||||
memval |= QSPI_SETUP_RD_NORMAL;
|
||||
break;
|
||||
}
|
||||
memval |= ((msg->addr_width - 1) << QSPI_SETUP_ADDR_SHIFT |
|
||||
msg->dummy_bytes << QSPI_SETUP_DUMMY_SHIFT);
|
||||
ti_qspi_write(qspi, memval,
|
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QSPI_SPI_SETUP_REG(spi->chip_select));
|
||||
}
|
||||
|
||||
static int ti_qspi_spi_flash_read(struct spi_device *spi,
|
||||
struct spi_flash_read_message *msg)
|
||||
{
|
||||
struct ti_qspi *qspi = spi_master_get_devdata(spi->master);
|
||||
int ret = 0;
|
||||
|
||||
mutex_lock(&qspi->list_lock);
|
||||
|
||||
if (!qspi->mmap_enabled)
|
||||
ti_qspi_enable_memory_map(spi);
|
||||
ti_qspi_setup_mmap_read(spi, msg);
|
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memcpy_fromio(msg->buf, qspi->mmap_base + msg->from, msg->len);
|
||||
msg->retlen = msg->len;
|
||||
|
||||
mutex_unlock(&qspi->list_lock);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int ti_qspi_start_transfer_one(struct spi_master *master,
|
||||
struct spi_message *m)
|
||||
{
|
||||
|
|
@ -398,6 +475,9 @@ static int ti_qspi_start_transfer_one(struct spi_master *master,
|
|||
|
||||
mutex_lock(&qspi->list_lock);
|
||||
|
||||
if (qspi->mmap_enabled)
|
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ti_qspi_disable_memory_map(spi);
|
||||
|
||||
list_for_each_entry(t, &m->transfers, transfer_list) {
|
||||
qspi->cmd |= QSPI_WLEN(t->bits_per_word);
|
||||
|
||||
|
|
@ -441,7 +521,7 @@ static int ti_qspi_probe(struct platform_device *pdev)
|
|||
{
|
||||
struct ti_qspi *qspi;
|
||||
struct spi_master *master;
|
||||
struct resource *r, *res_ctrl, *res_mmap;
|
||||
struct resource *r, *res_mmap;
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
u32 max_freq;
|
||||
int ret = 0, num_cs, irq;
|
||||
|
|
@ -487,16 +567,6 @@ static int ti_qspi_probe(struct platform_device *pdev)
|
|||
}
|
||||
}
|
||||
|
||||
res_ctrl = platform_get_resource_byname(pdev,
|
||||
IORESOURCE_MEM, "qspi_ctrlmod");
|
||||
if (res_ctrl == NULL) {
|
||||
res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 2);
|
||||
if (res_ctrl == NULL) {
|
||||
dev_dbg(&pdev->dev,
|
||||
"control module resources not required\n");
|
||||
}
|
||||
}
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
dev_err(&pdev->dev, "no irq resource?\n");
|
||||
|
|
@ -511,20 +581,31 @@ static int ti_qspi_probe(struct platform_device *pdev)
|
|||
goto free_master;
|
||||
}
|
||||
|
||||
if (res_ctrl) {
|
||||
qspi->ctrl_mod = true;
|
||||
qspi->ctrl_base = devm_ioremap_resource(&pdev->dev, res_ctrl);
|
||||
if (IS_ERR(qspi->ctrl_base)) {
|
||||
ret = PTR_ERR(qspi->ctrl_base);
|
||||
goto free_master;
|
||||
if (res_mmap) {
|
||||
qspi->mmap_base = devm_ioremap_resource(&pdev->dev,
|
||||
res_mmap);
|
||||
master->spi_flash_read = ti_qspi_spi_flash_read;
|
||||
if (IS_ERR(qspi->mmap_base)) {
|
||||
dev_err(&pdev->dev,
|
||||
"falling back to PIO mode\n");
|
||||
master->spi_flash_read = NULL;
|
||||
}
|
||||
}
|
||||
qspi->mmap_enabled = false;
|
||||
|
||||
if (res_mmap) {
|
||||
qspi->mmap_base = devm_ioremap_resource(&pdev->dev, res_mmap);
|
||||
if (IS_ERR(qspi->mmap_base)) {
|
||||
ret = PTR_ERR(qspi->mmap_base);
|
||||
goto free_master;
|
||||
if (of_property_read_bool(np, "syscon-chipselects")) {
|
||||
qspi->ctrl_base =
|
||||
syscon_regmap_lookup_by_phandle(np,
|
||||
"syscon-chipselects");
|
||||
if (IS_ERR(qspi->ctrl_base))
|
||||
return PTR_ERR(qspi->ctrl_base);
|
||||
ret = of_property_read_u32_index(np,
|
||||
"syscon-chipselects",
|
||||
1, &qspi->ctrl_reg);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev,
|
||||
"couldn't get ctrl_mod reg index\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -604,6 +604,10 @@ extern struct spi_master *spi_busnum_to_master(u16 busnum);
|
|||
* SPI resource management while processing a SPI message
|
||||
*/
|
||||
|
||||
typedef void (*spi_res_release_t)(struct spi_master *master,
|
||||
struct spi_message *msg,
|
||||
void *res);
|
||||
|
||||
/**
|
||||
* struct spi_res - spi resource management structure
|
||||
* @entry: list entry
|
||||
|
|
@ -613,9 +617,6 @@ extern struct spi_master *spi_busnum_to_master(u16 busnum);
|
|||
* this is based on ideas from devres, but focused on life-cycle
|
||||
* management during spi_message processing
|
||||
*/
|
||||
typedef void (*spi_res_release_t)(struct spi_master *master,
|
||||
struct spi_message *msg,
|
||||
void *res);
|
||||
struct spi_res {
|
||||
struct list_head entry;
|
||||
spi_res_release_t release;
|
||||
|
|
|
|||
Загрузка…
Ссылка в новой задаче