ACPICA: Fix writes to optional PM1B registers
On read, shift B register bits above the A bits. On write, shift B bits down to zero before writing the B register. New: acpi_hw_read_multiple, acpi_hw_write_multiple. These two functions now transparently handle the (possible) split registers for PM1 Status, Enable, and Control. Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
This commit is contained in:
Bob Moore
Len Brown
Родитель
d3319d1717
Коммит
c520abadbc
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@ -51,6 +51,17 @@
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#define _COMPONENT ACPI_HARDWARE
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ACPI_MODULE_NAME("hwregs")
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/* Local Prototypes */
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static acpi_status
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acpi_hw_read_multiple(u32 *value,
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struct acpi_generic_address *register_a,
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struct acpi_generic_address *register_b);
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static acpi_status
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acpi_hw_write_multiple(u32 value,
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struct acpi_generic_address *register_a,
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struct acpi_generic_address *register_b);
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/*******************************************************************************
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*
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* FUNCTION: acpi_hw_clear_acpi_status
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@ -63,6 +74,7 @@ ACPI_MODULE_NAME("hwregs")
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* THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED
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*
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******************************************************************************/
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acpi_status acpi_hw_clear_acpi_status(void)
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{
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acpi_status status;
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@ -143,64 +155,49 @@ struct acpi_bit_register_info *acpi_hw_get_bit_register_info(u32 register_id)
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acpi_status
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acpi_hw_register_read(u32 register_id, u32 * return_value)
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{
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u32 value1 = 0;
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u32 value2 = 0;
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u32 value = 0;
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acpi_status status;
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ACPI_FUNCTION_TRACE(hw_register_read);
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switch (register_id) {
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case ACPI_REGISTER_PM1_STATUS: /* 16-bit access */
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case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */
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status = acpi_read(&value1, &acpi_gbl_xpm1a_status);
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if (ACPI_FAILURE(status)) {
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goto exit;
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}
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/* PM1B is optional */
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status = acpi_read(&value2, &acpi_gbl_xpm1b_status);
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value1 |= value2;
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status = acpi_hw_read_multiple(&value,
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&acpi_gbl_xpm1a_status,
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&acpi_gbl_xpm1b_status);
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break;
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case ACPI_REGISTER_PM1_ENABLE: /* 16-bit access */
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case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */
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status = acpi_read(&value1, &acpi_gbl_xpm1a_enable);
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if (ACPI_FAILURE(status)) {
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goto exit;
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}
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/* PM1B is optional */
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status = acpi_read(&value2, &acpi_gbl_xpm1b_enable);
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value1 |= value2;
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status = acpi_hw_read_multiple(&value,
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&acpi_gbl_xpm1a_enable,
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&acpi_gbl_xpm1b_enable);
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break;
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case ACPI_REGISTER_PM1_CONTROL: /* 16-bit access */
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case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */
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status = acpi_read(&value1, &acpi_gbl_FADT.xpm1a_control_block);
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if (ACPI_FAILURE(status)) {
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goto exit;
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}
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status = acpi_read(&value2, &acpi_gbl_FADT.xpm1b_control_block);
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value1 |= value2;
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status = acpi_hw_read_multiple(&value,
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&acpi_gbl_FADT.
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xpm1a_control_block,
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&acpi_gbl_FADT.
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xpm1b_control_block);
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break;
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case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */
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status = acpi_read(&value1, &acpi_gbl_FADT.xpm2_control_block);
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status = acpi_read(&value, &acpi_gbl_FADT.xpm2_control_block);
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break;
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case ACPI_REGISTER_PM_TIMER: /* 32-bit access */
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status = acpi_read(&value1, &acpi_gbl_FADT.xpm_timer_block);
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status = acpi_read(&value, &acpi_gbl_FADT.xpm_timer_block);
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break;
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case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */
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status =
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acpi_os_read_port(acpi_gbl_FADT.smi_command, &value1, 8);
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acpi_os_read_port(acpi_gbl_FADT.smi_command, &value, 8);
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break;
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default:
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@ -209,10 +206,8 @@ acpi_hw_register_read(u32 register_id, u32 * return_value)
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break;
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}
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exit:
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if (ACPI_SUCCESS(status)) {
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*return_value = value1;
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*return_value = value;
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}
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return_ACPI_STATUS(status);
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@ -252,12 +247,13 @@ acpi_status acpi_hw_register_write(u32 register_id, u32 value)
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ACPI_FUNCTION_TRACE(hw_register_write);
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switch (register_id) {
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case ACPI_REGISTER_PM1_STATUS: /* 16-bit access */
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case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */
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/* Perform a read first to preserve certain bits (per ACPI spec) */
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status = acpi_hw_register_read(ACPI_REGISTER_PM1_STATUS,
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&read_value);
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status = acpi_hw_read_multiple(&read_value,
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&acpi_gbl_xpm1a_status,
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&acpi_gbl_xpm1b_status);
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if (ACPI_FAILURE(status)) {
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goto exit;
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}
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@ -269,35 +265,29 @@ acpi_status acpi_hw_register_write(u32 register_id, u32 value)
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/* Now we can write the data */
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status = acpi_write(value, &acpi_gbl_xpm1a_status);
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if (ACPI_FAILURE(status)) {
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goto exit;
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}
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/* PM1B is optional */
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status = acpi_write(value, &acpi_gbl_xpm1b_status);
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status = acpi_hw_write_multiple(value,
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&acpi_gbl_xpm1a_status,
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&acpi_gbl_xpm1b_status);
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break;
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case ACPI_REGISTER_PM1_ENABLE: /* 16-bit access */
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case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access */
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status = acpi_write(value, &acpi_gbl_xpm1a_enable);
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if (ACPI_FAILURE(status)) {
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goto exit;
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}
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/* PM1B is optional */
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status = acpi_write(value, &acpi_gbl_xpm1b_enable);
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status = acpi_hw_write_multiple(value,
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&acpi_gbl_xpm1a_enable,
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&acpi_gbl_xpm1b_enable);
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break;
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case ACPI_REGISTER_PM1_CONTROL: /* 16-bit access */
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case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */
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/*
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* Perform a read first to preserve certain bits (per ACPI spec)
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* Note: This includes SCI_EN, we never want to change this bit
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*/
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status = acpi_hw_register_read(ACPI_REGISTER_PM1_CONTROL,
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&read_value);
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status = acpi_hw_read_multiple(&read_value,
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&acpi_gbl_FADT.
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xpm1a_control_block,
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&acpi_gbl_FADT.
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xpm1b_control_block);
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if (ACPI_FAILURE(status)) {
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goto exit;
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}
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@ -309,12 +299,11 @@ acpi_status acpi_hw_register_write(u32 register_id, u32 value)
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/* Now we can write the data */
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status = acpi_write(value, &acpi_gbl_FADT.xpm1a_control_block);
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if (ACPI_FAILURE(status)) {
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goto exit;
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}
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status = acpi_write(value, &acpi_gbl_FADT.xpm1b_control_block);
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status = acpi_hw_write_multiple(value,
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&acpi_gbl_FADT.
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xpm1a_control_block,
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&acpi_gbl_FADT.
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xpm1b_control_block);
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break;
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case ACPI_REGISTER_PM1A_CONTROL: /* 16-bit access */
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@ -346,6 +335,7 @@ acpi_status acpi_hw_register_write(u32 register_id, u32 value)
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break;
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default:
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ACPI_ERROR((AE_INFO, "Unknown Register ID: %X", register_id));
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status = AE_BAD_PARAMETER;
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break;
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}
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@ -353,3 +343,88 @@ acpi_status acpi_hw_register_write(u32 register_id, u32 value)
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exit:
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return_ACPI_STATUS(status);
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}
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/******************************************************************************
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*
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* FUNCTION: acpi_hw_read_multiple
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*
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* PARAMETERS: Value - Where the register value is returned
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* register_a - First ACPI register (required)
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* register_b - Second ACPI register (optional)
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*
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* RETURN: Status
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*
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* DESCRIPTION: Read from the specified two-part ACPI register (such as PM1 A/B)
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*
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******************************************************************************/
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static acpi_status
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acpi_hw_read_multiple(u32 *value,
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struct acpi_generic_address *register_a,
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struct acpi_generic_address *register_b)
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{
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u32 value_a = 0;
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u32 value_b = 0;
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acpi_status status;
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/* The first register is always required */
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status = acpi_read(&value_a, register_a);
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if (ACPI_FAILURE(status)) {
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return (status);
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}
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/* Second register is optional */
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if (register_b->address) {
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status = acpi_read(&value_b, register_b);
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if (ACPI_FAILURE(status)) {
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return (status);
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}
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}
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/* Shift the B bits above the A bits */
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*value = value_a | (value_b << register_a->bit_width);
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return (AE_OK);
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}
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/******************************************************************************
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*
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* FUNCTION: acpi_hw_write_multiple
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*
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* PARAMETERS: Value - The value to write
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* register_a - First ACPI register (required)
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* register_b - Second ACPI register (optional)
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*
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* RETURN: Status
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*
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* DESCRIPTION: Write to the specified two-part ACPI register (such as PM1 A/B)
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*
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******************************************************************************/
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static acpi_status
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acpi_hw_write_multiple(u32 value,
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struct acpi_generic_address *register_a,
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struct acpi_generic_address *register_b)
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{
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acpi_status status;
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/* The first register is always required */
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status = acpi_write(value, register_a);
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if (ACPI_FAILURE(status)) {
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return (status);
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}
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/* Second register is optional */
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if (register_b->address) {
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/* Normalize the B bits before write */
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status = acpi_write(value >> register_a->bit_width, register_b);
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}
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return (status);
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}
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