Merge branch 'lpc32xx/devel' into next/soc
* lpc32xx/devel: (22 commits) ARM: LPC32xx: Move i2s1 dma enabling to clock.c ARM: LPC32xx: Move uart6 irda disable to serial.c ARM: LPC32xx: Cleanup board init, remove duplicate clock init ARM: LPC32xx: Remove spi chip definitions ARM: LPC32xx: Remove spi chipselect request from board init ARM: LPC32xx: Add dt settings to the at25 node ARM: LPC32xx: Build arch dtbs ARM: LPC32xx: Fix lpc32xx.dtsi status property: "disable" -> "disabled" ARM: LPC32xx: Remove mach specific ARCH_NR_GPIOS, use default ARM: LPC32xx: High Speed UART configuration via DT ARM: LPC32xx: DT conversion of Standard UARTs ARM: LPC32xx: DTS adjustment for using pl18x primecell ARM: LPC32xx: Add MMC controller support ARM: LPC32xx: Defconfig update ARM: LPC32xx: Clock adjustment for key matrix controller ARM: LPC32xx: DTS adjustment for key matrix controller ARM: LPC32xx: Add dts for EA3250 reference board ARM: LPC32xx: Adjust dtsi file for MLC controller configuration ARM: LPC32xx: Add DMA configuration to platform data ARM: LPC32xx: Remove SLC controller initialization from platform init ...
This commit is contained in:
Olof Johansson
Коммит
c536294134
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@ -1019,8 +1019,6 @@ source "arch/arm/mach-kirkwood/Kconfig"
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source "arch/arm/mach-ks8695/Kconfig"
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source "arch/arm/mach-lpc32xx/Kconfig"
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source "arch/arm/mach-msm/Kconfig"
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source "arch/arm/mach-mv78xx0/Kconfig"
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|
|
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|
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@ -0,0 +1,157 @@
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|||
/*
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* Embedded Artists LPC3250 board
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*
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* Copyright 2012 Roland Stigge <stigge@antcom.de>
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*
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* The code contained herein is licensed under the GNU General Public
|
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* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
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*
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||||
* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/dts-v1/;
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/include/ "lpc32xx.dtsi"
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/ {
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model = "Embedded Artists LPC3250 board based on NXP LPC3250";
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compatible = "ea,ea3250", "nxp,lpc3250";
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#address-cells = <1>;
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#size-cells = <1>;
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memory {
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device_type = "memory";
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reg = <0 0x4000000>;
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};
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ahb {
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mac: ethernet@31060000 {
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phy-mode = "rmii";
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use-iram;
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};
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/* Here, choose exactly one from: ohci, usbd */
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ohci@31020000 {
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transceiver = <&isp1301>;
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status = "okay";
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};
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/*
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usbd@31020000 {
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transceiver = <&isp1301>;
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status = "okay";
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};
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*/
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/* 128MB Flash via SLC NAND controller */
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slc: flash@20020000 {
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status = "okay";
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#address-cells = <1>;
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#size-cells = <1>;
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nxp,wdr-clks = <14>;
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nxp,wwidth = <260000000>;
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nxp,whold = <104000000>;
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nxp,wsetup = <200000000>;
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nxp,rdr-clks = <14>;
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nxp,rwidth = <34666666>;
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nxp,rhold = <104000000>;
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nxp,rsetup = <200000000>;
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nand-on-flash-bbt;
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gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
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mtd0@00000000 {
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label = "ea3250-boot";
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reg = <0x00000000 0x00080000>;
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read-only;
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};
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mtd1@00080000 {
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label = "ea3250-uboot";
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reg = <0x00080000 0x000c0000>;
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read-only;
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};
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mtd2@00140000 {
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label = "ea3250-kernel";
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reg = <0x00140000 0x00400000>;
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};
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mtd3@00540000 {
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label = "ea3250-rootfs";
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reg = <0x00540000 0x07ac0000>;
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};
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};
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apb {
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uart5: serial@40090000 {
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status = "okay";
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};
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uart3: serial@40080000 {
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status = "okay";
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};
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uart6: serial@40098000 {
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status = "okay";
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};
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i2c1: i2c@400A0000 {
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clock-frequency = <100000>;
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eeprom@50 {
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compatible = "at,24c256";
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reg = <0x50>;
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};
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|
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eeprom@57 {
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compatible = "at,24c64";
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reg = <0x57>;
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};
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|
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uda1380: uda1380@18 {
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compatible = "nxp,uda1380";
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reg = <0x18>;
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power-gpio = <&gpio 0x59 0>;
|
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reset-gpio = <&gpio 0x51 0>;
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dac-clk = "wspll";
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};
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|
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pca9532: pca9532@60 {
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compatible = "nxp,pca9532";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x60>;
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};
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};
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i2c2: i2c@400A8000 {
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clock-frequency = <100000>;
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};
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i2cusb: i2c@31020300 {
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clock-frequency = <100000>;
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|
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isp1301: usb-transceiver@2d {
|
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compatible = "nxp,isp1301";
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reg = <0x2d>;
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};
|
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};
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sd@20098000 {
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wp-gpios = <&pca9532 5 0>;
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cd-gpios = <&pca9532 4 0>;
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cd-inverted;
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bus-width = <4>;
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status = "okay";
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};
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};
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fab {
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uart1: serial@40014000 {
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status = "okay";
|
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};
|
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};
|
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};
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};
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@ -35,13 +35,14 @@
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slc: flash@20020000 {
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compatible = "nxp,lpc3220-slc";
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reg = <0x20020000 0x1000>;
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status = "disable";
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status = "disabled";
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};
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mlc: flash@200B0000 {
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mlc: flash@200a8000 {
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compatible = "nxp,lpc3220-mlc";
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reg = <0x200B0000 0x1000>;
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status = "disable";
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reg = <0x200a8000 0x11000>;
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interrupts = <11 0>;
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status = "disabled";
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};
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dma@31000000 {
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@ -57,21 +58,21 @@
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compatible = "nxp,ohci-nxp", "usb-ohci";
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reg = <0x31020000 0x300>;
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interrupts = <0x3b 0>;
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status = "disable";
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status = "disabled";
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};
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|
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usbd@31020000 {
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compatible = "nxp,lpc3220-udc";
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reg = <0x31020000 0x300>;
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interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
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status = "disable";
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status = "disabled";
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||||
};
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||||
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clcd@31040000 {
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compatible = "arm,pl110", "arm,primecell";
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reg = <0x31040000 0x1000>;
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interrupts = <0x0e 0>;
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status = "disable";
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status = "disabled";
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};
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|
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mac: ethernet@31060000 {
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@ -114,9 +115,10 @@
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};
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sd@20098000 {
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compatible = "arm,pl180", "arm,primecell";
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compatible = "arm,pl18x", "arm,primecell";
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reg = <0x20098000 0x1000>;
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interrupts = <0x0f 0>, <0x0d 0>;
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status = "disabled";
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};
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i2s1: i2s@2009C000 {
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@ -124,24 +126,42 @@
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reg = <0x2009C000 0x1000>;
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};
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/* UART5 first since it is the default console, ttyS0 */
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uart5: serial@40090000 {
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/* actually, ns16550a w/ 64 byte fifos! */
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compatible = "nxp,lpc3220-uart";
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reg = <0x40090000 0x1000>;
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interrupts = <9 0>;
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clock-frequency = <13000000>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart3: serial@40080000 {
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compatible = "nxp,serial";
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compatible = "nxp,lpc3220-uart";
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reg = <0x40080000 0x1000>;
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interrupts = <7 0>;
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clock-frequency = <13000000>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart4: serial@40088000 {
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compatible = "nxp,serial";
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compatible = "nxp,lpc3220-uart";
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reg = <0x40088000 0x1000>;
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};
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uart5: serial@40090000 {
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compatible = "nxp,serial";
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reg = <0x40090000 0x1000>;
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interrupts = <8 0>;
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clock-frequency = <13000000>;
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reg-shift = <2>;
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status = "disabled";
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};
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uart6: serial@40098000 {
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compatible = "nxp,serial";
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compatible = "nxp,lpc3220-uart";
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reg = <0x40098000 0x1000>;
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interrupts = <10 0>;
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clock-frequency = <13000000>;
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reg-shift = <2>;
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status = "disabled";
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};
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i2c1: i2c@400A0000 {
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@ -192,18 +212,24 @@
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};
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uart1: serial@40014000 {
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compatible = "nxp,serial";
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compatible = "nxp,lpc3220-hsuart";
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reg = <0x40014000 0x1000>;
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interrupts = <26 0>;
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status = "disabled";
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};
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uart2: serial@40018000 {
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compatible = "nxp,serial";
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compatible = "nxp,lpc3220-hsuart";
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reg = <0x40018000 0x1000>;
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interrupts = <25 0>;
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status = "disabled";
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};
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uart7: serial@4001C000 {
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compatible = "nxp,serial";
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reg = <0x4001C000 0x1000>;
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uart7: serial@4001c000 {
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compatible = "nxp,lpc3220-hsuart";
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reg = <0x4001c000 0x1000>;
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interrupts = <24 0>;
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status = "disabled";
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};
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rtc@40024000 {
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@ -235,19 +261,21 @@
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compatible = "nxp,lpc3220-adc";
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reg = <0x40048000 0x1000>;
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interrupts = <0x27 0>;
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status = "disable";
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status = "disabled";
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};
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tsc@40048000 {
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compatible = "nxp,lpc3220-tsc";
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reg = <0x40048000 0x1000>;
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interrupts = <0x27 0>;
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status = "disable";
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status = "disabled";
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};
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key@40050000 {
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compatible = "nxp,lpc3220-key";
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reg = <0x40050000 0x1000>;
|
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interrupts = <54 0>;
|
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status = "disabled";
|
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};
|
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|
||||
};
|
||||
|
|
|
|||
|
|
@ -54,6 +54,17 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
nxp,wdr-clks = <14>;
|
||||
nxp,wwidth = <40000000>;
|
||||
nxp,whold = <100000000>;
|
||||
nxp,wsetup = <100000000>;
|
||||
nxp,rdr-clks = <14>;
|
||||
nxp,rwidth = <40000000>;
|
||||
nxp,rhold = <66666666>;
|
||||
nxp,rsetup = <100000000>;
|
||||
nand-on-flash-bbt;
|
||||
gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
|
||||
|
||||
mtd0@00000000 {
|
||||
label = "phy3250-boot";
|
||||
reg = <0x00000000 0x00064000>;
|
||||
|
|
@ -83,6 +94,14 @@
|
|||
};
|
||||
|
||||
apb {
|
||||
uart5: serial@40090000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart3: serial@40080000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c1: i2c@400A0000 {
|
||||
clock-frequency = <100000>;
|
||||
|
||||
|
|
@ -114,16 +133,58 @@
|
|||
};
|
||||
|
||||
ssp0: ssp@20084000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pl022,num-chipselects = <1>;
|
||||
cs-gpios = <&gpio 3 5 0>;
|
||||
|
||||
eeprom: at25@0 {
|
||||
pl022,hierarchy = <0>;
|
||||
pl022,interface = <0>;
|
||||
pl022,slave-tx-disable = <0>;
|
||||
pl022,com-mode = <0>;
|
||||
pl022,rx-level-trig = <1>;
|
||||
pl022,tx-level-trig = <1>;
|
||||
pl022,ctrl-len = <11>;
|
||||
pl022,wait-state = <0>;
|
||||
pl022,duplex = <0>;
|
||||
|
||||
at25,byte-len = <0x8000>;
|
||||
at25,addr-mode = <2>;
|
||||
at25,page-size = <64>;
|
||||
|
||||
compatible = "atmel,at25";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <5000000>;
|
||||
};
|
||||
};
|
||||
|
||||
sd@20098000 {
|
||||
wp-gpios = <&gpio 3 0 0>;
|
||||
cd-gpios = <&gpio 3 1 0>;
|
||||
cd-inverted;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
fab {
|
||||
uart2: serial@40018000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
tsc@40048000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
key@40050000 {
|
||||
status = "okay";
|
||||
keypad,num-rows = <1>;
|
||||
keypad,num-columns = <1>;
|
||||
nxp,debounce-delay-ms = <3>;
|
||||
nxp,scan-delay-ms = <34>;
|
||||
linux,keymap = <0x00000002>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,7 @@
|
|||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=16
|
||||
|
|
@ -16,8 +18,6 @@ CONFIG_MODULE_UNLOAD=y
|
|||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_ARCH_LPC32XX=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_PREEMPT=y
|
||||
CONFIG_AEABI=y
|
||||
CONFIG_ZBOOT_ROM_TEXT=0x0
|
||||
|
|
@ -52,13 +52,17 @@ CONFIG_MTD=y
|
|||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_M25P80=y
|
||||
CONFIG_MTD_NAND=y
|
||||
CONFIG_MTD_NAND_MUSEUM_IDS=y
|
||||
CONFIG_MTD_NAND_SLC_LPC32XX=y
|
||||
CONFIG_MTD_NAND_MLC_LPC32XX=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_CRYPTOLOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_COUNT=1
|
||||
CONFIG_BLK_DEV_RAM_SIZE=16384
|
||||
CONFIG_EEPROM_AT24=y
|
||||
CONFIG_EEPROM_AT25=y
|
||||
CONFIG_SCSI=y
|
||||
CONFIG_BLK_DEV_SD=y
|
||||
|
|
@ -79,16 +83,22 @@ CONFIG_LPC_ENET=y
|
|||
# CONFIG_NET_VENDOR_STMICRO is not set
|
||||
CONFIG_SMSC_PHY=y
|
||||
# CONFIG_WLAN is not set
|
||||
CONFIG_INPUT_MATRIXKMAP=y
|
||||
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
|
||||
CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
|
||||
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
|
||||
CONFIG_INPUT_EVDEV=y
|
||||
# CONFIG_KEYBOARD_ATKBD is not set
|
||||
CONFIG_KEYBOARD_LPC32XX=y
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
CONFIG_INPUT_TOUCHSCREEN=y
|
||||
CONFIG_TOUCHSCREEN_LPC32XX=y
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
# CONFIG_LEGACY_PTYS is not set
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_HS_LPC32XX=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
|
|
@ -96,7 +106,8 @@ CONFIG_I2C_PNX=y
|
|||
CONFIG_SPI=y
|
||||
CONFIG_SPI_PL022=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_SENSORS_DS620=y
|
||||
CONFIG_SENSORS_MAX6639=y
|
||||
CONFIG_WATCHDOG=y
|
||||
CONFIG_PNX4008_WATCHDOG=y
|
||||
CONFIG_FB=y
|
||||
|
|
@ -133,6 +144,8 @@ CONFIG_MMC=y
|
|||
CONFIG_MMC_ARMMMCI=y
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_LEDS_PCA9532=y
|
||||
CONFIG_LEDS_PCA9532_GPIO=y
|
||||
CONFIG_LEDS_GPIO=y
|
||||
CONFIG_LEDS_TRIGGERS=y
|
||||
CONFIG_LEDS_TRIGGER_TIMER=y
|
||||
|
|
@ -146,10 +159,10 @@ CONFIG_RTC_DRV_DS1374=y
|
|||
CONFIG_RTC_DRV_PCF8563=y
|
||||
CONFIG_RTC_DRV_LPC32XX=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_AMBA_PL08X=y
|
||||
CONFIG_STAGING=y
|
||||
CONFIG_IIO=y
|
||||
CONFIG_LPC32XX_ADC=y
|
||||
CONFIG_MAX517=y
|
||||
CONFIG_IIO=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_AUTOFS4_FS=y
|
||||
CONFIG_MSDOS_FS=y
|
||||
|
|
@ -159,7 +172,6 @@ CONFIG_JFFS2_FS=y
|
|||
CONFIG_JFFS2_FS_WBUF_VERIFY=y
|
||||
CONFIG_CRAMFS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_ASCII=y
|
||||
|
|
|
|||
|
|
@ -1,32 +0,0 @@
|
|||
if ARCH_LPC32XX
|
||||
|
||||
menu "Individual UART enable selections"
|
||||
|
||||
config ARCH_LPC32XX_UART3_SELECT
|
||||
bool "Add support for standard UART3"
|
||||
help
|
||||
Adds support for standard UART 3 when the 8250 serial support
|
||||
is enabled.
|
||||
|
||||
config ARCH_LPC32XX_UART4_SELECT
|
||||
bool "Add support for standard UART4"
|
||||
help
|
||||
Adds support for standard UART 4 when the 8250 serial support
|
||||
is enabled.
|
||||
|
||||
config ARCH_LPC32XX_UART5_SELECT
|
||||
bool "Add support for standard UART5"
|
||||
default y
|
||||
help
|
||||
Adds support for standard UART 5 when the 8250 serial support
|
||||
is enabled.
|
||||
|
||||
config ARCH_LPC32XX_UART6_SELECT
|
||||
bool "Add support for standard UART6"
|
||||
help
|
||||
Adds support for standard UART 6 when the 8250 serial support
|
||||
is enabled.
|
||||
|
||||
endmenu
|
||||
|
||||
endif
|
||||
|
|
@ -2,3 +2,4 @@
|
|||
params_phys-y := 0x80000100
|
||||
initrd_phys-y := 0x82000000
|
||||
|
||||
dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
|
||||
|
|
|
|||
|
|
@ -691,10 +691,21 @@ static struct clk clk_nand = {
|
|||
.parent = &clk_hclk,
|
||||
.enable = local_onoff_enable,
|
||||
.enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL,
|
||||
.enable_mask = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN,
|
||||
.enable_mask = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN |
|
||||
LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
|
||||
.get_rate = local_return_parent_rate,
|
||||
};
|
||||
|
||||
static struct clk clk_nand_mlc = {
|
||||
.parent = &clk_hclk,
|
||||
.enable = local_onoff_enable,
|
||||
.enable_reg = LPC32XX_CLKPWR_NAND_CLK_CTRL,
|
||||
.enable_mask = LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN |
|
||||
LPC32XX_CLKPWR_NANDCLK_DMA_INT |
|
||||
LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC,
|
||||
.get_rate = local_return_parent_rate,
|
||||
};
|
||||
|
||||
static struct clk clk_i2s0 = {
|
||||
.parent = &clk_hclk,
|
||||
.enable = local_onoff_enable,
|
||||
|
|
@ -707,7 +718,8 @@ static struct clk clk_i2s1 = {
|
|||
.parent = &clk_hclk,
|
||||
.enable = local_onoff_enable,
|
||||
.enable_reg = LPC32XX_CLKPWR_I2S_CLK_CTRL,
|
||||
.enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN,
|
||||
.enable_mask = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN |
|
||||
LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA,
|
||||
.get_rate = local_return_parent_rate,
|
||||
};
|
||||
|
||||
|
|
@ -1120,8 +1132,9 @@ static struct clk_lookup lookups[] = {
|
|||
CLKDEV_INIT("31020300.i2c", NULL, &clk_i2c2),
|
||||
CLKDEV_INIT("dev:ssp0", NULL, &clk_ssp0),
|
||||
CLKDEV_INIT("dev:ssp1", NULL, &clk_ssp1),
|
||||
CLKDEV_INIT("lpc32xx_keys.0", NULL, &clk_kscan),
|
||||
CLKDEV_INIT("lpc32xx-nand.0", "nand_ck", &clk_nand),
|
||||
CLKDEV_INIT("40050000.key", NULL, &clk_kscan),
|
||||
CLKDEV_INIT("20020000.flash", NULL, &clk_nand),
|
||||
CLKDEV_INIT("200a8000.flash", NULL, &clk_nand_mlc),
|
||||
CLKDEV_INIT("40048000.adc", NULL, &clk_adc),
|
||||
CLKDEV_INIT(NULL, "i2s0_ck", &clk_i2s0),
|
||||
CLKDEV_INIT(NULL, "i2s1_ck", &clk_i2s1),
|
||||
|
|
|
|||
|
|
@ -3,6 +3,4 @@
|
|||
|
||||
#include "gpio-lpc32xx.h"
|
||||
|
||||
#define ARCH_NR_GPIOS (LPC32XX_GPO_P3_GRP + LPC32XX_GPO_P3_MAX)
|
||||
|
||||
#endif /* __MACH_GPIO_H */
|
||||
|
|
|
|||
|
|
@ -30,12 +30,13 @@
|
|||
#include <linux/amba/bus.h>
|
||||
#include <linux/amba/clcd.h>
|
||||
#include <linux/amba/pl022.h>
|
||||
#include <linux/amba/pl08x.h>
|
||||
#include <linux/amba/mmci.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/amba/pl08x.h>
|
||||
|
||||
#include <asm/setup.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
|
@ -50,9 +51,12 @@
|
|||
/*
|
||||
* Mapped GPIOLIB GPIOs
|
||||
*/
|
||||
#define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
|
||||
#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
|
||||
#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
|
||||
#define SPI0_CS_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
|
||||
#define LCD_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
|
||||
#define BKL_POWER_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
|
||||
#define MMC_PWR_ENABLE_GPIO LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5)
|
||||
#define MMC_CD_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 1)
|
||||
#define MMC_WP_GPIO LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 0)
|
||||
|
||||
/*
|
||||
* AMBA LCD controller
|
||||
|
|
@ -158,24 +162,6 @@ static struct clcd_board lpc32xx_clcd_data = {
|
|||
/*
|
||||
* AMBA SSP (SPI)
|
||||
*/
|
||||
static void phy3250_spi_cs_set(u32 control)
|
||||
{
|
||||
gpio_set_value(SPI0_CS_GPIO, (int) control);
|
||||
}
|
||||
|
||||
static struct pl022_config_chip spi0_chip_info = {
|
||||
.com_mode = INTERRUPT_TRANSFER,
|
||||
.iface = SSP_INTERFACE_MOTOROLA_SPI,
|
||||
.hierarchy = SSP_MASTER,
|
||||
.slave_tx_disable = 0,
|
||||
.rx_lev_trig = SSP_RX_4_OR_MORE_ELEM,
|
||||
.tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC,
|
||||
.ctrl_len = SSP_BITS_8,
|
||||
.wait_state = SSP_MWIRE_WAIT_ZERO,
|
||||
.duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
|
||||
.cs_control = phy3250_spi_cs_set,
|
||||
};
|
||||
|
||||
static struct pl022_ssp_controller lpc32xx_ssp0_data = {
|
||||
.bus_id = 0,
|
||||
.num_chipselect = 1,
|
||||
|
|
@ -188,45 +174,57 @@ static struct pl022_ssp_controller lpc32xx_ssp1_data = {
|
|||
.enable_dma = 0,
|
||||
};
|
||||
|
||||
/* AT25 driver registration */
|
||||
static int __init phy3250_spi_board_register(void)
|
||||
static struct pl08x_channel_data pl08x_slave_channels[] = {
|
||||
{
|
||||
.bus_id = "nand-slc",
|
||||
.min_signal = 1, /* SLC NAND Flash */
|
||||
.max_signal = 1,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
},
|
||||
{
|
||||
.bus_id = "nand-mlc",
|
||||
.min_signal = 12, /* MLC NAND Flash */
|
||||
.max_signal = 12,
|
||||
.periph_buses = PL08X_AHB1,
|
||||
},
|
||||
};
|
||||
|
||||
/* NOTE: These will change, according to RMK */
|
||||
static int pl08x_get_signal(struct pl08x_dma_chan *ch)
|
||||
{
|
||||
return ch->cd->min_signal;
|
||||
}
|
||||
|
||||
static void pl08x_put_signal(struct pl08x_dma_chan *ch)
|
||||
{
|
||||
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
|
||||
static struct spi_board_info info[] = {
|
||||
{
|
||||
.modalias = "spidev",
|
||||
.max_speed_hz = 5000000,
|
||||
.bus_num = 0,
|
||||
.chip_select = 0,
|
||||
.controller_data = &spi0_chip_info,
|
||||
},
|
||||
};
|
||||
|
||||
#else
|
||||
static struct spi_eeprom eeprom = {
|
||||
.name = "at25256a",
|
||||
.byte_len = 0x8000,
|
||||
.page_size = 64,
|
||||
.flags = EE_ADDR2,
|
||||
};
|
||||
|
||||
static struct spi_board_info info[] = {
|
||||
{
|
||||
.modalias = "at25",
|
||||
.max_speed_hz = 5000000,
|
||||
.bus_num = 0,
|
||||
.chip_select = 0,
|
||||
.mode = SPI_MODE_0,
|
||||
.platform_data = &eeprom,
|
||||
.controller_data = &spi0_chip_info,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
return spi_register_board_info(info, ARRAY_SIZE(info));
|
||||
}
|
||||
arch_initcall(phy3250_spi_board_register);
|
||||
|
||||
static struct pl08x_platform_data pl08x_pd = {
|
||||
.slave_channels = &pl08x_slave_channels[0],
|
||||
.num_slave_channels = ARRAY_SIZE(pl08x_slave_channels),
|
||||
.get_signal = pl08x_get_signal,
|
||||
.put_signal = pl08x_put_signal,
|
||||
.lli_buses = PL08X_AHB1,
|
||||
.mem_buses = PL08X_AHB1,
|
||||
};
|
||||
|
||||
static int mmc_handle_ios(struct device *dev, struct mmc_ios *ios)
|
||||
{
|
||||
/* Only on and off are supported */
|
||||
if (ios->power_mode == MMC_POWER_OFF)
|
||||
gpio_set_value(MMC_PWR_ENABLE_GPIO, 0);
|
||||
else
|
||||
gpio_set_value(MMC_PWR_ENABLE_GPIO, 1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct mmci_platform_data lpc32xx_mmci_data = {
|
||||
.ocr_mask = MMC_VDD_30_31 | MMC_VDD_31_32 |
|
||||
MMC_VDD_32_33 | MMC_VDD_33_34,
|
||||
.ios_handler = mmc_handle_ios,
|
||||
.dma_filter = NULL,
|
||||
/* No DMA for now since AMBA PL080 dmaengine driver only does scatter
|
||||
* gather, and the MMCI driver doesn't do it this way */
|
||||
};
|
||||
|
||||
static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
|
||||
|
|
@ -234,6 +232,8 @@ static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
|
|||
OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data),
|
||||
OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data),
|
||||
OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
|
||||
OF_DEV_AUXDATA("arm,pl18x", 0x20098000, "20098000.sd",
|
||||
&lpc32xx_mmci_data),
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
@ -241,10 +241,6 @@ static void __init lpc3250_machine_init(void)
|
|||
{
|
||||
u32 tmp;
|
||||
|
||||
/* Setup SLC NAND controller muxing */
|
||||
__raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
|
||||
LPC32XX_CLKPWR_NAND_CLK_CTRL);
|
||||
|
||||
/* Setup LCD muxing to RGB565 */
|
||||
tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
|
||||
~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
|
||||
|
|
@ -264,34 +260,12 @@ static void __init lpc3250_machine_init(void)
|
|||
LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
|
||||
__raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
|
||||
|
||||
/* Disable IrDA pulsing support on UART6 */
|
||||
tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
|
||||
tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
|
||||
__raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
|
||||
|
||||
/* Enable DMA for I2S1 channel */
|
||||
tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL);
|
||||
tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA;
|
||||
__raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL);
|
||||
|
||||
lpc32xx_serial_init();
|
||||
|
||||
/*
|
||||
* AMBA peripheral clocks need to be enabled prior to AMBA device
|
||||
* detection or a data fault will occur, so enable the clocks
|
||||
* here.
|
||||
*/
|
||||
tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
|
||||
__raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
|
||||
LPC32XX_CLKPWR_LCDCLK_CTRL);
|
||||
|
||||
tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
|
||||
__raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
|
||||
LPC32XX_CLKPWR_SSP_CLK_CTRL);
|
||||
|
||||
tmp = __raw_readl(LPC32XX_CLKPWR_DMA_CLK_CTRL);
|
||||
__raw_writel((tmp | LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN),
|
||||
LPC32XX_CLKPWR_DMA_CLK_CTRL);
|
||||
tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
|
||||
tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
|
||||
LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
|
||||
__raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
|
||||
|
||||
/* Test clock needed for UDA1380 initial init */
|
||||
__raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
|
||||
|
|
@ -302,12 +276,10 @@ static void __init lpc3250_machine_init(void)
|
|||
lpc32xx_auxdata_lookup, NULL);
|
||||
|
||||
/* Register GPIOs used on this board */
|
||||
if (gpio_request(SPI0_CS_GPIO, "spi0 cs"))
|
||||
printk(KERN_ERR "Error requesting gpio %u",
|
||||
SPI0_CS_GPIO);
|
||||
else if (gpio_direction_output(SPI0_CS_GPIO, 1))
|
||||
printk(KERN_ERR "Error setting gpio %u to output",
|
||||
SPI0_CS_GPIO);
|
||||
if (gpio_request(MMC_PWR_ENABLE_GPIO, "mmc_power_en"))
|
||||
pr_err("Error requesting gpio %u", MMC_PWR_ENABLE_GPIO);
|
||||
else if (gpio_direction_output(MMC_PWR_ENABLE_GPIO, 1))
|
||||
pr_err("Error setting gpio %u to output", MMC_PWR_ENABLE_GPIO);
|
||||
}
|
||||
|
||||
static char const *lpc32xx_dt_compat[] __initdata = {
|
||||
|
|
|
|||
|
|
@ -31,59 +31,6 @@
|
|||
|
||||
#define LPC32XX_SUART_FIFO_SIZE 64
|
||||
|
||||
/* Standard 8250/16550 compatible serial ports */
|
||||
static struct plat_serial8250_port serial_std_platform_data[] = {
|
||||
#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT
|
||||
{
|
||||
.membase = io_p2v(LPC32XX_UART5_BASE),
|
||||
.mapbase = LPC32XX_UART5_BASE,
|
||||
.irq = IRQ_LPC32XX_UART_IIR5,
|
||||
.uartclk = LPC32XX_MAIN_OSC_FREQ,
|
||||
.regshift = 2,
|
||||
.iotype = UPIO_MEM32,
|
||||
.flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
|
||||
UPF_SKIP_TEST,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
|
||||
{
|
||||
.membase = io_p2v(LPC32XX_UART3_BASE),
|
||||
.mapbase = LPC32XX_UART3_BASE,
|
||||
.irq = IRQ_LPC32XX_UART_IIR3,
|
||||
.uartclk = LPC32XX_MAIN_OSC_FREQ,
|
||||
.regshift = 2,
|
||||
.iotype = UPIO_MEM32,
|
||||
.flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
|
||||
UPF_SKIP_TEST,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
|
||||
{
|
||||
.membase = io_p2v(LPC32XX_UART4_BASE),
|
||||
.mapbase = LPC32XX_UART4_BASE,
|
||||
.irq = IRQ_LPC32XX_UART_IIR4,
|
||||
.uartclk = LPC32XX_MAIN_OSC_FREQ,
|
||||
.regshift = 2,
|
||||
.iotype = UPIO_MEM32,
|
||||
.flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
|
||||
UPF_SKIP_TEST,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
|
||||
{
|
||||
.membase = io_p2v(LPC32XX_UART6_BASE),
|
||||
.mapbase = LPC32XX_UART6_BASE,
|
||||
.irq = IRQ_LPC32XX_UART_IIR6,
|
||||
.uartclk = LPC32XX_MAIN_OSC_FREQ,
|
||||
.regshift = 2,
|
||||
.iotype = UPIO_MEM32,
|
||||
.flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
|
||||
UPF_SKIP_TEST,
|
||||
},
|
||||
#endif
|
||||
{ },
|
||||
};
|
||||
|
||||
struct uartinit {
|
||||
char *uart_ck_name;
|
||||
u32 ck_mode_mask;
|
||||
|
|
@ -92,7 +39,6 @@ struct uartinit {
|
|||
};
|
||||
|
||||
static struct uartinit uartinit_data[] __initdata = {
|
||||
#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT
|
||||
{
|
||||
.uart_ck_name = "uart5_ck",
|
||||
.ck_mode_mask =
|
||||
|
|
@ -100,8 +46,6 @@ static struct uartinit uartinit_data[] __initdata = {
|
|||
.pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,
|
||||
.mapbase = LPC32XX_UART5_BASE,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
|
||||
{
|
||||
.uart_ck_name = "uart3_ck",
|
||||
.ck_mode_mask =
|
||||
|
|
@ -109,8 +53,6 @@ static struct uartinit uartinit_data[] __initdata = {
|
|||
.pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,
|
||||
.mapbase = LPC32XX_UART3_BASE,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
|
||||
{
|
||||
.uart_ck_name = "uart4_ck",
|
||||
.ck_mode_mask =
|
||||
|
|
@ -118,8 +60,6 @@ static struct uartinit uartinit_data[] __initdata = {
|
|||
.pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,
|
||||
.mapbase = LPC32XX_UART4_BASE,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
|
||||
{
|
||||
.uart_ck_name = "uart6_ck",
|
||||
.ck_mode_mask =
|
||||
|
|
@ -127,19 +67,6 @@ static struct uartinit uartinit_data[] __initdata = {
|
|||
.pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,
|
||||
.mapbase = LPC32XX_UART6_BASE,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct platform_device serial_std_platform_device = {
|
||||
.name = "serial8250",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = serial_std_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *lpc32xx_serial_devs[] __initdata = {
|
||||
&serial_std_platform_device,
|
||||
};
|
||||
|
||||
void __init lpc32xx_serial_init(void)
|
||||
|
|
@ -156,15 +83,8 @@ void __init lpc32xx_serial_init(void)
|
|||
clk = clk_get(NULL, uartinit_data[i].uart_ck_name);
|
||||
if (!IS_ERR(clk)) {
|
||||
clk_enable(clk);
|
||||
serial_std_platform_data[i].uartclk =
|
||||
clk_get_rate(clk);
|
||||
}
|
||||
|
||||
/* Fall back on main osc rate if clock rate return fails */
|
||||
if (serial_std_platform_data[i].uartclk == 0)
|
||||
serial_std_platform_data[i].uartclk =
|
||||
LPC32XX_MAIN_OSC_FREQ;
|
||||
|
||||
/* Setup UART clock modes for all UARTs, disable autoclock */
|
||||
clkmodes |= uartinit_data[i].ck_mode_mask;
|
||||
|
||||
|
|
@ -189,7 +109,7 @@ void __init lpc32xx_serial_init(void)
|
|||
__raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);
|
||||
for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
|
||||
/* Force a flush of the RX FIFOs to work around a HW bug */
|
||||
puart = serial_std_platform_data[i].mapbase;
|
||||
puart = uartinit_data[i].mapbase;
|
||||
__raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
|
||||
__raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
|
||||
j = LPC32XX_SUART_FIFO_SIZE;
|
||||
|
|
@ -198,11 +118,13 @@ void __init lpc32xx_serial_init(void)
|
|||
__raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
|
||||
}
|
||||
|
||||
/* Disable IrDA pulsing support on UART6 */
|
||||
tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
|
||||
tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
|
||||
__raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
|
||||
|
||||
/* Disable UART5->USB transparent mode or USB won't work */
|
||||
tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
|
||||
tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
|
||||
__raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
|
||||
|
||||
platform_add_devices(lpc32xx_serial_devs,
|
||||
ARRAY_SIZE(lpc32xx_serial_devs));
|
||||
}
|
||||
|
|
|
|||
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