drm/vc4: Add support for the BCM2711 HVS5
The HVS found in the BCM2711 is slightly different from the previous generations. Most notably, the display list layout changes a bit, the LBM doesn't have the same size and the formats ordering for some formats is swapped. Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Tested-by: Chanwoo Choi <cw00.choi@samsung.com> Tested-by: Hoegeun Kwon <hoegeun.kwon@samsung.com> Tested-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Eric Anholt <eric@anholt.net> Link: https://patchwork.freedesktop.org/patch/msgid/1d02fab3b916d639c2dc05608c117bbd8230ebe8.1599120059.git-series.maxime@cerno.tech
This commit is contained in:
Dave Stevenson
Maxime Ripard
Родитель
3ac929e722
Коммит
c54619b0bf
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@ -329,7 +329,11 @@ struct vc4_hvs {
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spinlock_t mm_lock;
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struct drm_mm_node mitchell_netravali_filter;
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struct debugfs_regset32 regset;
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/* HVS version 5 flag, therefore requires updated dlist structures */
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bool hvs5;
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};
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struct vc4_plane {
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@ -277,11 +277,19 @@ void vc4_hvs_atomic_enable(struct drm_crtc *crtc,
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* mode.
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*/
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dispctrl = SCALER_DISPCTRLX_ENABLE;
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dispctrl |= VC4_SET_FIELD(mode->hdisplay,
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SCALER_DISPCTRLX_WIDTH) |
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VC4_SET_FIELD(mode->vdisplay,
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SCALER_DISPCTRLX_HEIGHT) |
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(oneshot ? SCALER_DISPCTRLX_ONESHOT : 0);
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if (!vc4->hvs->hvs5)
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dispctrl |= VC4_SET_FIELD(mode->hdisplay,
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SCALER_DISPCTRLX_WIDTH) |
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VC4_SET_FIELD(mode->vdisplay,
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SCALER_DISPCTRLX_HEIGHT) |
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(oneshot ? SCALER_DISPCTRLX_ONESHOT : 0);
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else
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dispctrl |= VC4_SET_FIELD(mode->hdisplay,
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SCALER5_DISPCTRLX_WIDTH) |
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VC4_SET_FIELD(mode->vdisplay,
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SCALER5_DISPCTRLX_HEIGHT) |
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(oneshot ? SCALER5_DISPCTRLX_ONESHOT : 0);
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HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel), dispctrl);
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}
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@ -521,6 +529,9 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
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hvs->pdev = pdev;
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if (of_device_is_compatible(pdev->dev.of_node, "brcm,bcm2711-hvs"))
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hvs->hvs5 = true;
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hvs->regs = vc4_ioremap_regs(pdev, 0);
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if (IS_ERR(hvs->regs))
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return PTR_ERR(hvs->regs);
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@ -529,7 +540,10 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
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hvs->regset.regs = hvs_regs;
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hvs->regset.nregs = ARRAY_SIZE(hvs_regs);
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hvs->dlist = hvs->regs + SCALER_DLIST_START;
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if (!hvs->hvs5)
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hvs->dlist = hvs->regs + SCALER_DLIST_START;
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else
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hvs->dlist = hvs->regs + SCALER5_DLIST_START;
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spin_lock_init(&hvs->mm_lock);
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@ -547,7 +561,12 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)
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* between planes when they don't overlap on the screen, but
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* for now we just allocate globally.
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*/
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drm_mm_init(&hvs->lbm_mm, 0, 96 * 1024);
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if (!hvs->hvs5)
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/* 96kB */
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drm_mm_init(&hvs->lbm_mm, 0, 96 * 1024);
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else
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/* 70k words */
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drm_mm_init(&hvs->lbm_mm, 0, 70 * 2 * 1024);
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/* Upload filter kernels. We only have the one for now, so we
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* keep it around for the lifetime of the driver.
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@ -632,6 +651,7 @@ static int vc4_hvs_dev_remove(struct platform_device *pdev)
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}
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static const struct of_device_id vc4_hvs_dt_match[] = {
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{ .compatible = "brcm,bcm2711-hvs" },
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{ .compatible = "brcm,bcm2835-hvs" },
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{}
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};
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@ -32,45 +32,60 @@ static const struct hvs_format {
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u32 drm; /* DRM_FORMAT_* */
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u32 hvs; /* HVS_FORMAT_* */
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u32 pixel_order;
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u32 pixel_order_hvs5;
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} hvs_formats[] = {
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{
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.drm = DRM_FORMAT_XRGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
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.drm = DRM_FORMAT_XRGB8888,
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.hvs = HVS_PIXEL_FORMAT_RGBA8888,
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.pixel_order = HVS_PIXEL_ORDER_ABGR,
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.pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
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},
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{
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.drm = DRM_FORMAT_ARGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
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.drm = DRM_FORMAT_ARGB8888,
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.hvs = HVS_PIXEL_FORMAT_RGBA8888,
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.pixel_order = HVS_PIXEL_ORDER_ABGR,
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.pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB,
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},
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{
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.drm = DRM_FORMAT_ABGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
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.drm = DRM_FORMAT_ABGR8888,
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.hvs = HVS_PIXEL_FORMAT_RGBA8888,
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.pixel_order = HVS_PIXEL_ORDER_ARGB,
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.pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR,
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},
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{
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.drm = DRM_FORMAT_XBGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
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.drm = DRM_FORMAT_XBGR8888,
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.hvs = HVS_PIXEL_FORMAT_RGBA8888,
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.pixel_order = HVS_PIXEL_ORDER_ARGB,
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.pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR,
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},
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{
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.drm = DRM_FORMAT_RGB565, .hvs = HVS_PIXEL_FORMAT_RGB565,
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.drm = DRM_FORMAT_RGB565,
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.hvs = HVS_PIXEL_FORMAT_RGB565,
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.pixel_order = HVS_PIXEL_ORDER_XRGB,
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},
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{
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.drm = DRM_FORMAT_BGR565, .hvs = HVS_PIXEL_FORMAT_RGB565,
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.drm = DRM_FORMAT_BGR565,
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.hvs = HVS_PIXEL_FORMAT_RGB565,
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.pixel_order = HVS_PIXEL_ORDER_XBGR,
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},
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{
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.drm = DRM_FORMAT_ARGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
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.drm = DRM_FORMAT_ARGB1555,
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.hvs = HVS_PIXEL_FORMAT_RGBA5551,
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.pixel_order = HVS_PIXEL_ORDER_ABGR,
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},
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{
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.drm = DRM_FORMAT_XRGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
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.drm = DRM_FORMAT_XRGB1555,
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.hvs = HVS_PIXEL_FORMAT_RGBA5551,
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.pixel_order = HVS_PIXEL_ORDER_ABGR,
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},
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{
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.drm = DRM_FORMAT_RGB888, .hvs = HVS_PIXEL_FORMAT_RGB888,
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.drm = DRM_FORMAT_RGB888,
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.hvs = HVS_PIXEL_FORMAT_RGB888,
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.pixel_order = HVS_PIXEL_ORDER_XRGB,
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},
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{
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.drm = DRM_FORMAT_BGR888, .hvs = HVS_PIXEL_FORMAT_RGB888,
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.drm = DRM_FORMAT_BGR888,
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.hvs = HVS_PIXEL_FORMAT_RGB888,
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.pixel_order = HVS_PIXEL_ORDER_XBGR,
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},
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{
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@ -776,35 +791,6 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
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return -EINVAL;
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}
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/* Control word */
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vc4_dlist_write(vc4_state,
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SCALER_CTL0_VALID |
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(rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) |
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(rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) |
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VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
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(format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
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(hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
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VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
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(vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
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VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
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VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
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/* Position Word 0: Image Positions and Alpha Value */
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vc4_state->pos0_offset = vc4_state->dlist_count;
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vc4_dlist_write(vc4_state,
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VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
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VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
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VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
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/* Position Word 1: Scaled Image Dimensions. */
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if (!vc4_state->is_unity) {
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vc4_dlist_write(vc4_state,
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VC4_SET_FIELD(vc4_state->crtc_w,
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SCALER_POS1_SCL_WIDTH) |
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VC4_SET_FIELD(vc4_state->crtc_h,
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SCALER_POS1_SCL_HEIGHT));
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}
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/* Don't waste cycles mixing with plane alpha if the set alpha
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* is opaque or there is no per-pixel alpha information.
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* In any case we use the alpha property value as the fixed alpha.
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@ -812,20 +798,120 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
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mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE &&
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fb->format->has_alpha;
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/* Position Word 2: Source Image Size, Alpha */
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vc4_state->pos2_offset = vc4_state->dlist_count;
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vc4_dlist_write(vc4_state,
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VC4_SET_FIELD(fb->format->has_alpha ?
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SCALER_POS2_ALPHA_MODE_PIPELINE :
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SCALER_POS2_ALPHA_MODE_FIXED,
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SCALER_POS2_ALPHA_MODE) |
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(mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
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(fb->format->has_alpha ? SCALER_POS2_ALPHA_PREMULT : 0) |
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VC4_SET_FIELD(vc4_state->src_w[0], SCALER_POS2_WIDTH) |
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VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT));
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if (!vc4->hvs->hvs5) {
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/* Control word */
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vc4_dlist_write(vc4_state,
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SCALER_CTL0_VALID |
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(rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) |
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(rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) |
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VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
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(format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
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(hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
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VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
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(vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
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VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
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VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
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/* Position Word 3: Context. Written by the HVS. */
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vc4_dlist_write(vc4_state, 0xc0c0c0c0);
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/* Position Word 0: Image Positions and Alpha Value */
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vc4_state->pos0_offset = vc4_state->dlist_count;
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vc4_dlist_write(vc4_state,
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VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
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VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
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VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
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/* Position Word 1: Scaled Image Dimensions. */
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if (!vc4_state->is_unity) {
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vc4_dlist_write(vc4_state,
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VC4_SET_FIELD(vc4_state->crtc_w,
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SCALER_POS1_SCL_WIDTH) |
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VC4_SET_FIELD(vc4_state->crtc_h,
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SCALER_POS1_SCL_HEIGHT));
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}
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/* Position Word 2: Source Image Size, Alpha */
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vc4_state->pos2_offset = vc4_state->dlist_count;
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vc4_dlist_write(vc4_state,
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VC4_SET_FIELD(fb->format->has_alpha ?
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SCALER_POS2_ALPHA_MODE_PIPELINE :
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SCALER_POS2_ALPHA_MODE_FIXED,
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SCALER_POS2_ALPHA_MODE) |
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(mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
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(fb->format->has_alpha ?
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SCALER_POS2_ALPHA_PREMULT : 0) |
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VC4_SET_FIELD(vc4_state->src_w[0],
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SCALER_POS2_WIDTH) |
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VC4_SET_FIELD(vc4_state->src_h[0],
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SCALER_POS2_HEIGHT));
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/* Position Word 3: Context. Written by the HVS. */
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vc4_dlist_write(vc4_state, 0xc0c0c0c0);
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} else {
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u32 hvs_pixel_order = format->pixel_order;
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if (format->pixel_order_hvs5)
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hvs_pixel_order = format->pixel_order_hvs5;
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/* Control word */
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vc4_dlist_write(vc4_state,
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SCALER_CTL0_VALID |
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(hvs_pixel_order << SCALER_CTL0_ORDER_SHIFT) |
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(hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
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VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
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(vc4_state->is_unity ?
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SCALER5_CTL0_UNITY : 0) |
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VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
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VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1) |
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SCALER5_CTL0_ALPHA_EXPAND |
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SCALER5_CTL0_RGB_EXPAND);
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/* Position Word 0: Image Positions and Alpha Value */
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vc4_state->pos0_offset = vc4_state->dlist_count;
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vc4_dlist_write(vc4_state,
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(rotation & DRM_MODE_REFLECT_Y ?
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SCALER5_POS0_VFLIP : 0) |
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VC4_SET_FIELD(vc4_state->crtc_x,
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SCALER_POS0_START_X) |
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(rotation & DRM_MODE_REFLECT_X ?
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SCALER5_POS0_HFLIP : 0) |
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VC4_SET_FIELD(vc4_state->crtc_y,
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SCALER5_POS0_START_Y)
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);
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/* Control Word 2 */
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vc4_dlist_write(vc4_state,
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VC4_SET_FIELD(state->alpha >> 4,
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SCALER5_CTL2_ALPHA) |
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fb->format->has_alpha ?
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SCALER5_CTL2_ALPHA_PREMULT : 0 |
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(mix_plane_alpha ?
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SCALER5_CTL2_ALPHA_MIX : 0) |
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VC4_SET_FIELD(fb->format->has_alpha ?
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SCALER5_CTL2_ALPHA_MODE_PIPELINE :
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SCALER5_CTL2_ALPHA_MODE_FIXED,
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SCALER5_CTL2_ALPHA_MODE)
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);
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/* Position Word 1: Scaled Image Dimensions. */
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if (!vc4_state->is_unity) {
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vc4_dlist_write(vc4_state,
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VC4_SET_FIELD(vc4_state->crtc_w,
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SCALER_POS1_SCL_WIDTH) |
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VC4_SET_FIELD(vc4_state->crtc_h,
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SCALER_POS1_SCL_HEIGHT));
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}
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/* Position Word 2: Source Image Size */
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vc4_state->pos2_offset = vc4_state->dlist_count;
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vc4_dlist_write(vc4_state,
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VC4_SET_FIELD(vc4_state->src_w[0],
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SCALER5_POS2_WIDTH) |
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VC4_SET_FIELD(vc4_state->src_h[0],
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SCALER5_POS2_HEIGHT));
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/* Position Word 3: Context. Written by the HVS. */
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vc4_dlist_write(vc4_state, 0xc0c0c0c0);
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}
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/* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers
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@ -1203,6 +1289,10 @@ static bool vc4_format_mod_supported(struct drm_plane *plane,
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default:
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return false;
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}
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case DRM_FORMAT_RGBX1010102:
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case DRM_FORMAT_BGRX1010102:
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case DRM_FORMAT_RGBA1010102:
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case DRM_FORMAT_BGRA1010102:
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case DRM_FORMAT_YUV422:
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case DRM_FORMAT_YVU422:
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case DRM_FORMAT_YUV420:
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@ -327,6 +327,20 @@
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# define SCALER_DISPCTRLX_HEIGHT_MASK VC4_MASK(11, 0)
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# define SCALER_DISPCTRLX_HEIGHT_SHIFT 0
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# define SCALER5_DISPCTRLX_WIDTH_MASK VC4_MASK(28, 16)
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# define SCALER5_DISPCTRLX_WIDTH_SHIFT 16
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/* Generates a single frame when VSTART is seen and stops at the last
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* pixel read from the FIFO.
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*/
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# define SCALER5_DISPCTRLX_ONESHOT BIT(15)
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/* Processes a single context in the dlist and then task switch,
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* instead of an entire line.
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*/
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# define SCALER5_DISPCTRLX_ONECTX_MASK VC4_MASK(14, 13)
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# define SCALER5_DISPCTRLX_ONECTX_SHIFT 13
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# define SCALER5_DISPCTRLX_HEIGHT_MASK VC4_MASK(12, 0)
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# define SCALER5_DISPCTRLX_HEIGHT_SHIFT 0
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#define SCALER_DISPBKGND0 0x00000044
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# define SCALER_DISPBKGND_AUTOHS BIT(31)
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# define SCALER_DISPBKGND_INTERLACE BIT(30)
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@ -460,6 +474,8 @@
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#define SCALER_DLIST_START 0x00002000
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#define SCALER_DLIST_SIZE 0x00004000
|
||||
|
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#define SCALER5_DLIST_START 0x00004000
|
||||
|
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#define VC4_HDMI_CORE_REV 0x000
|
||||
|
||||
#define VC4_HDMI_SW_RESET_CONTROL 0x004
|
||||
|
|
@ -825,6 +841,8 @@ enum hvs_pixel_format {
|
|||
HVS_PIXEL_FORMAT_PALETTE = 13,
|
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HVS_PIXEL_FORMAT_YUV444_RGB = 14,
|
||||
HVS_PIXEL_FORMAT_AYUV444_RGB = 15,
|
||||
HVS_PIXEL_FORMAT_RGBA1010102 = 16,
|
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HVS_PIXEL_FORMAT_YCBCR_10BIT = 17,
|
||||
};
|
||||
|
||||
/* Note: the LSB is the rightmost character shown. Only valid for
|
||||
|
|
@ -879,6 +897,10 @@ enum hvs_pixel_format {
|
|||
#define SCALER_CTL0_RGBA_EXPAND_MSB 2
|
||||
#define SCALER_CTL0_RGBA_EXPAND_ROUND 3
|
||||
|
||||
#define SCALER5_CTL0_ALPHA_EXPAND BIT(12)
|
||||
|
||||
#define SCALER5_CTL0_RGB_EXPAND BIT(11)
|
||||
|
||||
#define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8)
|
||||
#define SCALER_CTL0_SCL1_SHIFT 8
|
||||
|
||||
|
|
@ -896,10 +918,13 @@ enum hvs_pixel_format {
|
|||
|
||||
/* Set to indicate no scaling. */
|
||||
#define SCALER_CTL0_UNITY BIT(4)
|
||||
#define SCALER5_CTL0_UNITY BIT(15)
|
||||
|
||||
#define SCALER_CTL0_PIXEL_FORMAT_MASK VC4_MASK(3, 0)
|
||||
#define SCALER_CTL0_PIXEL_FORMAT_SHIFT 0
|
||||
|
||||
#define SCALER5_CTL0_PIXEL_FORMAT_MASK VC4_MASK(4, 0)
|
||||
|
||||
#define SCALER_POS0_FIXED_ALPHA_MASK VC4_MASK(31, 24)
|
||||
#define SCALER_POS0_FIXED_ALPHA_SHIFT 24
|
||||
|
||||
|
|
@ -909,12 +934,48 @@ enum hvs_pixel_format {
|
|||
#define SCALER_POS0_START_X_MASK VC4_MASK(11, 0)
|
||||
#define SCALER_POS0_START_X_SHIFT 0
|
||||
|
||||
#define SCALER5_POS0_START_Y_MASK VC4_MASK(27, 16)
|
||||
#define SCALER5_POS0_START_Y_SHIFT 16
|
||||
|
||||
#define SCALER5_POS0_START_X_MASK VC4_MASK(13, 0)
|
||||
#define SCALER5_POS0_START_X_SHIFT 0
|
||||
|
||||
#define SCALER5_POS0_VFLIP BIT(31)
|
||||
#define SCALER5_POS0_HFLIP BIT(15)
|
||||
|
||||
#define SCALER5_CTL2_ALPHA_MODE_MASK VC4_MASK(31, 30)
|
||||
#define SCALER5_CTL2_ALPHA_MODE_SHIFT 30
|
||||
#define SCALER5_CTL2_ALPHA_MODE_PIPELINE 0
|
||||
#define SCALER5_CTL2_ALPHA_MODE_FIXED 1
|
||||
#define SCALER5_CTL2_ALPHA_MODE_FIXED_NONZERO 2
|
||||
#define SCALER5_CTL2_ALPHA_MODE_FIXED_OVER_0x07 3
|
||||
|
||||
#define SCALER5_CTL2_ALPHA_PREMULT BIT(29)
|
||||
|
||||
#define SCALER5_CTL2_ALPHA_MIX BIT(28)
|
||||
|
||||
#define SCALER5_CTL2_ALPHA_LOC BIT(25)
|
||||
|
||||
#define SCALER5_CTL2_MAP_SEL_MASK VC4_MASK(18, 17)
|
||||
#define SCALER5_CTL2_MAP_SEL_SHIFT 17
|
||||
|
||||
#define SCALER5_CTL2_GAMMA BIT(16)
|
||||
|
||||
#define SCALER5_CTL2_ALPHA_MASK VC4_MASK(15, 4)
|
||||
#define SCALER5_CTL2_ALPHA_SHIFT 4
|
||||
|
||||
#define SCALER_POS1_SCL_HEIGHT_MASK VC4_MASK(27, 16)
|
||||
#define SCALER_POS1_SCL_HEIGHT_SHIFT 16
|
||||
|
||||
#define SCALER_POS1_SCL_WIDTH_MASK VC4_MASK(11, 0)
|
||||
#define SCALER_POS1_SCL_WIDTH_SHIFT 0
|
||||
|
||||
#define SCALER5_POS1_SCL_HEIGHT_MASK VC4_MASK(28, 16)
|
||||
#define SCALER5_POS1_SCL_HEIGHT_SHIFT 16
|
||||
|
||||
#define SCALER5_POS1_SCL_WIDTH_MASK VC4_MASK(12, 0)
|
||||
#define SCALER5_POS1_SCL_WIDTH_SHIFT 0
|
||||
|
||||
#define SCALER_POS2_ALPHA_MODE_MASK VC4_MASK(31, 30)
|
||||
#define SCALER_POS2_ALPHA_MODE_SHIFT 30
|
||||
#define SCALER_POS2_ALPHA_MODE_PIPELINE 0
|
||||
|
|
@ -930,6 +991,12 @@ enum hvs_pixel_format {
|
|||
#define SCALER_POS2_WIDTH_MASK VC4_MASK(11, 0)
|
||||
#define SCALER_POS2_WIDTH_SHIFT 0
|
||||
|
||||
#define SCALER5_POS2_HEIGHT_MASK VC4_MASK(28, 16)
|
||||
#define SCALER5_POS2_HEIGHT_SHIFT 16
|
||||
|
||||
#define SCALER5_POS2_WIDTH_MASK VC4_MASK(12, 0)
|
||||
#define SCALER5_POS2_WIDTH_SHIFT 0
|
||||
|
||||
/* Color Space Conversion words. Some values are S2.8 signed
|
||||
* integers, except that the 2 integer bits map as {0x0: 0, 0x1: 1,
|
||||
* 0x2: 2, 0x3: -1}
|
||||
|
|
|
|||
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