ARM: sunxi: Add support for Allwinner SUNXi SoCs sata to ahci_platform
This patch adds support for the ahci sata controler found on Allwinner A10 and A20 SoCs to the ahci_platform driver. Orignally written by Olliver Schinagl using the approach of having a platform device which probe method creates a new child platform device which gets driven by ahci_platform.c, as done by ahci_imx.c . Refactored by Hans de Goede to add most of the non sunxi specific functionality to ahci_platform.c and use a platform_data pointer from of_device_id for the sunxi specific bits. Signed-off-by: Olliver Schinagl <oliver@schinagl.nl> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Tejun Heo <tj@kernel.org>
This commit is contained in:
Olliver Schinagl
Tejun Heo
Родитель
648cb6fd83
Коммит
c5754b5220
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@ -4,7 +4,9 @@ SATA nodes are defined to describe on-chip Serial ATA controllers.
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Each SATA controller should have its own node.
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Required properties:
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- compatible : compatible list, contains "snps,spear-ahci"
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- compatible : compatible list, one of "snps,spear-ahci",
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"snps,exynos5440-ahci", "ibm,476gtr-ahci", or
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"allwinner,sun4i-a10-ahci"
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- interrupts : <interrupt mapping for SATA IRQ>
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- reg : <registers mapping>
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@ -13,10 +15,17 @@ Optional properties:
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- clocks : a list of phandle + clock specifier pairs
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- target-supply : regulator for SATA target power
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Example:
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Examples:
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sata@ffe08000 {
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compatible = "snps,spear-ahci";
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reg = <0xffe08000 0x1000>;
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interrupts = <115>;
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};
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ahci: sata@01c18000 {
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compatible = "allwinner,sun4i-a10-ahci";
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reg = <0x01c18000 0x1000>;
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interrupts = <56>;
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clocks = <&pll6 0>, <&ahb_gates 25>;
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target-supply = <®_ahci_5v>;
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};
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@ -106,6 +106,15 @@ config AHCI_IMX
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If unsure, say N.
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config AHCI_SUNXI
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tristate "Allwinner sunxi AHCI SATA support"
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depends on ARCH_SUNXI && SATA_AHCI_PLATFORM
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help
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This option enables support for the Allwinner sunxi SoC's
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onboard AHCI SATA.
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If unsure, say N.
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config SATA_FSL
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tristate "Freescale 3.0Gbps SATA support"
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depends on FSL_SOC
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@ -11,6 +11,7 @@ obj-$(CONFIG_SATA_SIL24) += sata_sil24.o
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obj-$(CONFIG_SATA_DWC) += sata_dwc_460ex.o
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obj-$(CONFIG_SATA_HIGHBANK) += sata_highbank.o libahci.o
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obj-$(CONFIG_AHCI_IMX) += ahci_imx.o
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obj-$(CONFIG_AHCI_SUNXI) += ahci_sunxi.o
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# SFF w/ custom DMA
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obj-$(CONFIG_PDC_ADMA) += pdc_adma.o
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@ -0,0 +1,249 @@
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/*
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* Allwinner sunxi AHCI SATA platform driver
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* Copyright 2013 Olliver Schinagl <oliver@schinagl.nl>
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* Copyright 2014 Hans de Goede <hdegoede@redhat.com>
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*
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* based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
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* Based on code from Allwinner Technology Co., Ltd. <www.allwinnertech.com>,
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* Daniel Wang <danielwang@allwinnertech.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/ahci_platform.h>
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#include <linux/clk.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/consumer.h>
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#include "ahci.h"
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#define AHCI_BISTAFR 0x00a0
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#define AHCI_BISTCR 0x00a4
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#define AHCI_BISTFCTR 0x00a8
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#define AHCI_BISTSR 0x00ac
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#define AHCI_BISTDECR 0x00b0
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#define AHCI_DIAGNR0 0x00b4
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#define AHCI_DIAGNR1 0x00b8
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#define AHCI_OOBR 0x00bc
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#define AHCI_PHYCS0R 0x00c0
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#define AHCI_PHYCS1R 0x00c4
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#define AHCI_PHYCS2R 0x00c8
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#define AHCI_TIMER1MS 0x00e0
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#define AHCI_GPARAM1R 0x00e8
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#define AHCI_GPARAM2R 0x00ec
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#define AHCI_PPARAMR 0x00f0
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#define AHCI_TESTR 0x00f4
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#define AHCI_VERSIONR 0x00f8
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#define AHCI_IDR 0x00fc
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#define AHCI_RWCR 0x00fc
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#define AHCI_P0DMACR 0x0170
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#define AHCI_P0PHYCR 0x0178
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#define AHCI_P0PHYSR 0x017c
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static void sunxi_clrbits(void __iomem *reg, u32 clr_val)
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{
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u32 reg_val;
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reg_val = readl(reg);
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reg_val &= ~(clr_val);
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writel(reg_val, reg);
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}
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static void sunxi_setbits(void __iomem *reg, u32 set_val)
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{
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u32 reg_val;
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reg_val = readl(reg);
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reg_val |= set_val;
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writel(reg_val, reg);
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}
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static void sunxi_clrsetbits(void __iomem *reg, u32 clr_val, u32 set_val)
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{
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u32 reg_val;
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reg_val = readl(reg);
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reg_val &= ~(clr_val);
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reg_val |= set_val;
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writel(reg_val, reg);
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}
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static u32 sunxi_getbits(void __iomem *reg, u8 mask, u8 shift)
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{
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return (readl(reg) >> shift) & mask;
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}
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static int ahci_sunxi_phy_init(struct device *dev, void __iomem *reg_base)
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{
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u32 reg_val;
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int timeout;
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/* This magic is from the original code */
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writel(0, reg_base + AHCI_RWCR);
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mdelay(5);
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sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(19));
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sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
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(0x7 << 24),
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(0x5 << 24) | BIT(23) | BIT(18));
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sunxi_clrsetbits(reg_base + AHCI_PHYCS1R,
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(0x3 << 16) | (0x1f << 8) | (0x3 << 6),
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(0x2 << 16) | (0x6 << 8) | (0x2 << 6));
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sunxi_setbits(reg_base + AHCI_PHYCS1R, BIT(28) | BIT(15));
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sunxi_clrbits(reg_base + AHCI_PHYCS1R, BIT(19));
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sunxi_clrsetbits(reg_base + AHCI_PHYCS0R,
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(0x7 << 20), (0x3 << 20));
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sunxi_clrsetbits(reg_base + AHCI_PHYCS2R,
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(0x1f << 5), (0x19 << 5));
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mdelay(5);
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sunxi_setbits(reg_base + AHCI_PHYCS0R, (0x1 << 19));
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timeout = 250; /* Power up takes aprox 50 us */
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do {
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reg_val = sunxi_getbits(reg_base + AHCI_PHYCS0R, 0x7, 28);
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if (reg_val == 0x02)
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break;
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if (--timeout == 0) {
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dev_err(dev, "PHY power up failed.\n");
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return -EIO;
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}
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udelay(1);
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} while (1);
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sunxi_setbits(reg_base + AHCI_PHYCS2R, (0x1 << 24));
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timeout = 100; /* Calibration takes aprox 10 us */
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do {
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reg_val = sunxi_getbits(reg_base + AHCI_PHYCS2R, 0x1, 24);
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if (reg_val == 0x00)
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break;
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if (--timeout == 0) {
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dev_err(dev, "PHY calibration failed.\n");
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return -EIO;
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}
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udelay(1);
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} while (1);
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mdelay(15);
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writel(0x7, reg_base + AHCI_RWCR);
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return 0;
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}
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static void ahci_sunxi_start_engine(struct ata_port *ap)
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{
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void __iomem *port_mmio = ahci_port_base(ap);
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struct ahci_host_priv *hpriv = ap->host->private_data;
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/* Setup DMA before DMA start */
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sunxi_clrsetbits(hpriv->mmio + AHCI_P0DMACR, 0x0000ff00, 0x00004400);
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/* Start DMA */
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sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START);
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}
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static const struct ata_port_info ahci_sunxi_port_info = {
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AHCI_HFLAGS(AHCI_HFLAG_32BIT_ONLY | AHCI_HFLAG_NO_MSI |
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AHCI_HFLAG_NO_PMP | AHCI_HFLAG_YES_NCQ),
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.flags = AHCI_FLAG_COMMON | ATA_FLAG_NCQ,
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.pio_mask = ATA_PIO4,
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.udma_mask = ATA_UDMA6,
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.port_ops = &ahci_platform_ops,
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};
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static int ahci_sunxi_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct ahci_host_priv *hpriv;
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int rc;
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hpriv = ahci_platform_get_resources(pdev);
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if (IS_ERR(hpriv))
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return PTR_ERR(hpriv);
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hpriv->start_engine = ahci_sunxi_start_engine;
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rc = ahci_platform_enable_resources(hpriv);
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if (rc)
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return rc;
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rc = ahci_sunxi_phy_init(dev, hpriv->mmio);
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if (rc)
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goto disable_resources;
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rc = ahci_platform_init_host(pdev, hpriv, &ahci_sunxi_port_info, 0, 0);
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if (rc)
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goto disable_resources;
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return 0;
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disable_resources:
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ahci_platform_disable_resources(hpriv);
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return rc;
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}
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#ifdef CONFIG_PM_SLEEP
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int ahci_sunxi_resume(struct device *dev)
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{
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struct ata_host *host = dev_get_drvdata(dev);
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struct ahci_host_priv *hpriv = host->private_data;
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int rc;
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rc = ahci_platform_enable_resources(hpriv);
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if (rc)
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return rc;
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rc = ahci_sunxi_phy_init(dev, hpriv->mmio);
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if (rc)
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goto disable_resources;
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rc = ahci_platform_resume_host(dev);
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if (rc)
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goto disable_resources;
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return 0;
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disable_resources:
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ahci_platform_disable_resources(hpriv);
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return rc;
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}
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#endif
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static SIMPLE_DEV_PM_OPS(ahci_sunxi_pm_ops, ahci_platform_suspend,
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ahci_sunxi_resume);
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static const struct of_device_id ahci_sunxi_of_match[] = {
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{ .compatible = "allwinner,sun4i-a10-ahci", },
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{ },
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};
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MODULE_DEVICE_TABLE(of, ahci_sunxi_of_match);
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static struct platform_driver ahci_sunxi_driver = {
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.probe = ahci_sunxi_probe,
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.remove = ata_platform_remove_one,
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.driver = {
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.name = "ahci-sunxi",
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.owner = THIS_MODULE,
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.of_match_table = ahci_sunxi_of_match,
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.pm = &ahci_sunxi_pm_ops,
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},
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};
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module_platform_driver(ahci_sunxi_driver);
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MODULE_DESCRIPTION("Allwinner sunxi AHCI SATA driver");
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MODULE_AUTHOR("Olliver Schinagl <oliver@schinagl.nl>");
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MODULE_LICENSE("GPL");
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