Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "Not a huge amount happening, some MAINTAINERS updates, radeon, vmwgfx and tegra fixes" * 'drm-fixes' of git://people.freedesktop.org/~airlied/linux: drm/vmwgfx: avoid null pointer dereference at failure paths drm/vmwgfx: Make sure backing mobs are cleared when allocated. Update driver date. drm/vmwgfx: Remove some unused surface formats drm/radeon: enable speaker allocation setup on dce3.2 drm/radeon: change audio enable logic drm/radeon: fix audio disable on dce6+ drm/radeon: free uvd ring on unload drm/radeon: disable pll sharing for DP on DCE4.1 drm/radeon: fix missing bo reservation drm/radeon: print the supported atpx function mask MAINTAINERS: update drm git tree entry MAINTAINERS: add entry for drm radeon driver drm/tegra: Add guard to avoid double disable/enable of RGB outputs gpu: host1x: do not check previously handled gathers drm/tegra: fix typo 'CONFIG_TEGRA_DRM_FBDEV'
This commit is contained in:
Linus Torvalds
Коммит
c59224d132
12
MAINTAINERS
12
MAINTAINERS
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|
@ -2848,12 +2848,22 @@ F: lib/kobj*
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DRM DRIVERS
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M: David Airlie <airlied@linux.ie>
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L: dri-devel@lists.freedesktop.org
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6.git
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T: git git://people.freedesktop.org/~airlied/linux
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S: Maintained
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F: drivers/gpu/drm/
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F: include/drm/
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F: include/uapi/drm/
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RADEON DRM DRIVERS
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M: Alex Deucher <alexander.deucher@amd.com>
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M: Christian König <christian.koenig@amd.com>
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L: dri-devel@lists.freedesktop.org
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T: git git://people.freedesktop.org/~agd5f/linux
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S: Supported
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F: drivers/gpu/drm/radeon/
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F: include/drm/radeon*
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F: include/uapi/drm/radeon*
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INTEL DRM DRIVERS (excluding Poulsbo, Moorestown and derivative chipsets)
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M: Daniel Vetter <daniel.vetter@ffwll.ch>
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M: Jani Nikula <jani.nikula@linux.intel.com>
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@ -1774,6 +1774,20 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
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return ATOM_PPLL1;
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DRM_ERROR("unable to allocate a PPLL\n");
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return ATOM_PPLL_INVALID;
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} else if (ASIC_IS_DCE41(rdev)) {
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/* Don't share PLLs on DCE4.1 chips */
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if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
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if (rdev->clock.dp_extclk)
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/* skip PPLL programming if using ext clock */
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return ATOM_PPLL_INVALID;
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}
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pll_in_use = radeon_get_pll_use_mask(crtc);
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if (!(pll_in_use & (1 << ATOM_PPLL1)))
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return ATOM_PPLL1;
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if (!(pll_in_use & (1 << ATOM_PPLL2)))
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return ATOM_PPLL2;
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DRM_ERROR("unable to allocate a PPLL\n");
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return ATOM_PPLL_INVALID;
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} else if (ASIC_IS_DCE4(rdev)) {
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/* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
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* depending on the asic:
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@ -1801,7 +1815,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
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if (pll != ATOM_PPLL_INVALID)
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return pll;
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}
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} else if (!ASIC_IS_DCE41(rdev)) { /* Don't share PLLs on DCE4.1 chips */
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} else {
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/* use the same PPLL for all monitors with the same clock */
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pll = radeon_get_shared_nondp_ppll(crtc);
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if (pll != ATOM_PPLL_INVALID)
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@ -278,13 +278,15 @@ static int dce6_audio_chipset_supported(struct radeon_device *rdev)
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return !ASIC_IS_NODCE(rdev);
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}
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static void dce6_audio_enable(struct radeon_device *rdev,
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struct r600_audio_pin *pin,
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bool enable)
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void dce6_audio_enable(struct radeon_device *rdev,
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struct r600_audio_pin *pin,
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bool enable)
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{
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if (!pin)
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return;
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WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL,
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AUDIO_ENABLED);
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DRM_INFO("%s audio %d support\n", enable ? "Enabling" : "Disabling", pin->id);
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enable ? AUDIO_ENABLED : 0);
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}
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static const u32 pin_offsets[7] =
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@ -323,7 +325,8 @@ int dce6_audio_init(struct radeon_device *rdev)
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rdev->audio.pin[i].connected = false;
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rdev->audio.pin[i].offset = pin_offsets[i];
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rdev->audio.pin[i].id = i;
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dce6_audio_enable(rdev, &rdev->audio.pin[i], true);
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/* disable audio. it will be set up later */
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dce6_audio_enable(rdev, &rdev->audio.pin[i], false);
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}
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return 0;
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@ -5475,9 +5475,9 @@ void evergreen_fini(struct radeon_device *rdev)
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radeon_wb_fini(rdev);
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radeon_ib_pool_fini(rdev);
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radeon_irq_kms_fini(rdev);
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evergreen_pcie_gart_fini(rdev);
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uvd_v1_0_fini(rdev);
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radeon_uvd_fini(rdev);
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evergreen_pcie_gart_fini(rdev);
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r600_vram_scratch_fini(rdev);
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radeon_gem_fini(rdev);
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radeon_fence_driver_fini(rdev);
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|
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@ -306,6 +306,15 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
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return;
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offset = dig->afmt->offset;
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/* disable audio prior to setting up hw */
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if (ASIC_IS_DCE6(rdev)) {
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dig->afmt->pin = dce6_audio_get_pin(rdev);
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dce6_audio_enable(rdev, dig->afmt->pin, false);
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} else {
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dig->afmt->pin = r600_audio_get_pin(rdev);
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r600_audio_enable(rdev, dig->afmt->pin, false);
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}
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evergreen_audio_set_dto(encoder, mode->clock);
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WREG32(HDMI_VBI_PACKET_CONTROL + offset,
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@ -409,12 +418,16 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
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WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
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WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
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WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);
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/* enable audio after to setting up hw */
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if (ASIC_IS_DCE6(rdev))
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dce6_audio_enable(rdev, dig->afmt->pin, true);
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else
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r600_audio_enable(rdev, dig->afmt->pin, true);
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}
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void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
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{
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struct drm_device *dev = encoder->dev;
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struct radeon_device *rdev = dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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@ -427,15 +440,6 @@ void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
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if (!enable && !dig->afmt->enabled)
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return;
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if (enable) {
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if (ASIC_IS_DCE6(rdev))
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dig->afmt->pin = dce6_audio_get_pin(rdev);
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else
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dig->afmt->pin = r600_audio_get_pin(rdev);
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} else {
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dig->afmt->pin = NULL;
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}
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dig->afmt->enabled = enable;
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DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
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|
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@ -142,12 +142,15 @@ void r600_audio_update_hdmi(struct work_struct *work)
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}
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/* enable the audio stream */
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static void r600_audio_enable(struct radeon_device *rdev,
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struct r600_audio_pin *pin,
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bool enable)
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void r600_audio_enable(struct radeon_device *rdev,
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struct r600_audio_pin *pin,
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bool enable)
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{
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u32 value = 0;
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if (!pin)
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return;
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if (ASIC_IS_DCE4(rdev)) {
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if (enable) {
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value |= 0x81000000; /* Required to enable audio */
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@ -158,7 +161,6 @@ static void r600_audio_enable(struct radeon_device *rdev,
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WREG32_P(R600_AUDIO_ENABLE,
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enable ? 0x81000000 : 0x0, ~0x81000000);
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}
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DRM_INFO("%s audio %d support\n", enable ? "Enabling" : "Disabling", pin->id);
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}
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/*
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@ -178,8 +180,8 @@ int r600_audio_init(struct radeon_device *rdev)
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rdev->audio.pin[0].status_bits = 0;
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rdev->audio.pin[0].category_code = 0;
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rdev->audio.pin[0].id = 0;
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r600_audio_enable(rdev, &rdev->audio.pin[0], true);
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/* disable audio. it will be set up later */
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r600_audio_enable(rdev, &rdev->audio.pin[0], false);
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return 0;
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}
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@ -329,9 +329,6 @@ static void dce3_2_afmt_write_speaker_allocation(struct drm_encoder *encoder)
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u8 *sadb;
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int sad_count;
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/* XXX: setting this register causes hangs on some asics */
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return;
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list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
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if (connector->encoder == encoder) {
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radeon_connector = to_radeon_connector(connector);
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@ -460,6 +457,10 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
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return;
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offset = dig->afmt->offset;
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/* disable audio prior to setting up hw */
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dig->afmt->pin = r600_audio_get_pin(rdev);
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r600_audio_enable(rdev, dig->afmt->pin, false);
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r600_audio_set_dto(encoder, mode->clock);
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WREG32(HDMI0_VBI_PACKET_CONTROL + offset,
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@ -531,6 +532,9 @@ void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mod
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WREG32(HDMI0_RAMP_CONTROL3 + offset, 0x00000001);
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r600_hdmi_audio_workaround(encoder);
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/* enable audio after to setting up hw */
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r600_audio_enable(rdev, dig->afmt->pin, true);
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}
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/*
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@ -651,11 +655,6 @@ void r600_hdmi_enable(struct drm_encoder *encoder, bool enable)
|
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if (!enable && !dig->afmt->enabled)
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return;
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|
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if (enable)
|
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dig->afmt->pin = r600_audio_get_pin(rdev);
|
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else
|
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dig->afmt->pin = NULL;
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/* Older chipsets require setting HDMI and routing manually */
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if (!ASIC_IS_DCE3(rdev)) {
|
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if (enable)
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|
|
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|
|
@ -2747,6 +2747,12 @@ int radeon_vm_bo_rmv(struct radeon_device *rdev,
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void r600_audio_update_hdmi(struct work_struct *work);
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struct r600_audio_pin *r600_audio_get_pin(struct radeon_device *rdev);
|
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struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev);
|
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void r600_audio_enable(struct radeon_device *rdev,
|
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struct r600_audio_pin *pin,
|
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bool enable);
|
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void dce6_audio_enable(struct radeon_device *rdev,
|
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struct r600_audio_pin *pin,
|
||||
bool enable);
|
||||
|
||||
/*
|
||||
* R600 vram scratch functions
|
||||
|
|
|
|||
|
|
@ -219,7 +219,8 @@ static int radeon_atpx_verify_interface(struct radeon_atpx *atpx)
|
|||
memcpy(&output, info->buffer.pointer, size);
|
||||
|
||||
/* TODO: check version? */
|
||||
printk("ATPX version %u\n", output.version);
|
||||
printk("ATPX version %u, functions 0x%08x\n",
|
||||
output.version, output.function_bits);
|
||||
|
||||
radeon_atpx_parse_functions(&atpx->functions, output.function_bits);
|
||||
|
||||
|
|
|
|||
|
|
@ -537,6 +537,10 @@ int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
|
|||
|
||||
radeon_vm_init(rdev, &fpriv->vm);
|
||||
|
||||
r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
/* map the ib pool buffer read only into
|
||||
* virtual address space */
|
||||
bo_va = radeon_vm_bo_add(rdev, &fpriv->vm,
|
||||
|
|
@ -544,6 +548,8 @@ int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
|
|||
r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET,
|
||||
RADEON_VM_PAGE_READABLE |
|
||||
RADEON_VM_PAGE_SNOOPED);
|
||||
|
||||
radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
|
||||
if (r) {
|
||||
radeon_vm_fini(rdev, &fpriv->vm);
|
||||
kfree(fpriv);
|
||||
|
|
|
|||
|
|
@ -171,6 +171,8 @@ void radeon_uvd_fini(struct radeon_device *rdev)
|
|||
|
||||
radeon_bo_unref(&rdev->uvd.vcpu_bo);
|
||||
|
||||
radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX]);
|
||||
|
||||
release_firmware(rdev->uvd_fw);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1955,9 +1955,9 @@ void rv770_fini(struct radeon_device *rdev)
|
|||
radeon_wb_fini(rdev);
|
||||
radeon_ib_pool_fini(rdev);
|
||||
radeon_irq_kms_fini(rdev);
|
||||
rv770_pcie_gart_fini(rdev);
|
||||
uvd_v1_0_fini(rdev);
|
||||
radeon_uvd_fini(rdev);
|
||||
rv770_pcie_gart_fini(rdev);
|
||||
r600_vram_scratch_fini(rdev);
|
||||
radeon_gem_fini(rdev);
|
||||
radeon_fence_driver_fini(rdev);
|
||||
|
|
|
|||
|
|
@ -104,7 +104,7 @@ static void tegra_drm_context_free(struct tegra_drm_context *context)
|
|||
|
||||
static void tegra_drm_lastclose(struct drm_device *drm)
|
||||
{
|
||||
#ifdef CONFIG_TEGRA_DRM_FBDEV
|
||||
#ifdef CONFIG_DRM_TEGRA_FBDEV
|
||||
struct tegra_drm *tegra = drm->dev_private;
|
||||
|
||||
tegra_fbdev_restore_mode(tegra->fbdev);
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@
|
|||
struct tegra_rgb {
|
||||
struct tegra_output output;
|
||||
struct tegra_dc *dc;
|
||||
bool enabled;
|
||||
|
||||
struct clk *clk_parent;
|
||||
struct clk *clk;
|
||||
|
|
@ -89,6 +90,9 @@ static int tegra_output_rgb_enable(struct tegra_output *output)
|
|||
struct tegra_rgb *rgb = to_rgb(output);
|
||||
unsigned long value;
|
||||
|
||||
if (rgb->enabled)
|
||||
return 0;
|
||||
|
||||
tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable));
|
||||
|
||||
value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
|
||||
|
|
@ -122,6 +126,8 @@ static int tegra_output_rgb_enable(struct tegra_output *output)
|
|||
tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
|
||||
tegra_dc_writel(rgb->dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
|
||||
|
||||
rgb->enabled = true;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -130,6 +136,9 @@ static int tegra_output_rgb_disable(struct tegra_output *output)
|
|||
struct tegra_rgb *rgb = to_rgb(output);
|
||||
unsigned long value;
|
||||
|
||||
if (!rgb->enabled)
|
||||
return 0;
|
||||
|
||||
value = tegra_dc_readl(rgb->dc, DC_CMD_DISPLAY_POWER_CONTROL);
|
||||
value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
|
||||
PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
|
||||
|
|
@ -144,6 +153,8 @@ static int tegra_output_rgb_disable(struct tegra_output *output)
|
|||
|
||||
tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
|
||||
|
||||
rgb->enabled = false;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -261,12 +261,7 @@ typedef enum SVGA3dSurfaceFormat {
|
|||
/* Planar video formats. */
|
||||
SVGA3D_YV12 = 121,
|
||||
|
||||
/* Shader constant formats. */
|
||||
SVGA3D_SURFACE_SHADERCONST_FLOAT = 122,
|
||||
SVGA3D_SURFACE_SHADERCONST_INT = 123,
|
||||
SVGA3D_SURFACE_SHADERCONST_BOOL = 124,
|
||||
|
||||
SVGA3D_FORMAT_MAX = 125,
|
||||
SVGA3D_FORMAT_MAX = 122,
|
||||
} SVGA3dSurfaceFormat;
|
||||
|
||||
typedef uint32 SVGA3dColor; /* a, r, g, b */
|
||||
|
|
|
|||
|
|
@ -40,7 +40,7 @@
|
|||
#include <drm/ttm/ttm_module.h>
|
||||
#include "vmwgfx_fence.h"
|
||||
|
||||
#define VMWGFX_DRIVER_DATE "20121114"
|
||||
#define VMWGFX_DRIVER_DATE "20140228"
|
||||
#define VMWGFX_DRIVER_MAJOR 2
|
||||
#define VMWGFX_DRIVER_MINOR 5
|
||||
#define VMWGFX_DRIVER_PATCHLEVEL 0
|
||||
|
|
|
|||
|
|
@ -188,18 +188,20 @@ static void vmw_takedown_otable_base(struct vmw_private *dev_priv,
|
|||
|
||||
bo = otable->page_table->pt_bo;
|
||||
cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
|
||||
if (unlikely(cmd == NULL))
|
||||
DRM_ERROR("Failed reserving FIFO space for OTable setup.\n");
|
||||
|
||||
memset(cmd, 0, sizeof(*cmd));
|
||||
cmd->header.id = SVGA_3D_CMD_SET_OTABLE_BASE;
|
||||
cmd->header.size = sizeof(cmd->body);
|
||||
cmd->body.type = type;
|
||||
cmd->body.baseAddress = 0;
|
||||
cmd->body.sizeInBytes = 0;
|
||||
cmd->body.validSizeInBytes = 0;
|
||||
cmd->body.ptDepth = SVGA3D_MOBFMT_INVALID;
|
||||
vmw_fifo_commit(dev_priv, sizeof(*cmd));
|
||||
if (unlikely(cmd == NULL)) {
|
||||
DRM_ERROR("Failed reserving FIFO space for OTable "
|
||||
"takedown.\n");
|
||||
} else {
|
||||
memset(cmd, 0, sizeof(*cmd));
|
||||
cmd->header.id = SVGA_3D_CMD_SET_OTABLE_BASE;
|
||||
cmd->header.size = sizeof(cmd->body);
|
||||
cmd->body.type = type;
|
||||
cmd->body.baseAddress = 0;
|
||||
cmd->body.sizeInBytes = 0;
|
||||
cmd->body.validSizeInBytes = 0;
|
||||
cmd->body.ptDepth = SVGA3D_MOBFMT_INVALID;
|
||||
vmw_fifo_commit(dev_priv, sizeof(*cmd));
|
||||
}
|
||||
|
||||
if (bo) {
|
||||
int ret;
|
||||
|
|
@ -562,11 +564,12 @@ void vmw_mob_unbind(struct vmw_private *dev_priv,
|
|||
if (unlikely(cmd == NULL)) {
|
||||
DRM_ERROR("Failed reserving FIFO space for Memory "
|
||||
"Object unbinding.\n");
|
||||
} else {
|
||||
cmd->header.id = SVGA_3D_CMD_DESTROY_GB_MOB;
|
||||
cmd->header.size = sizeof(cmd->body);
|
||||
cmd->body.mobid = mob->id;
|
||||
vmw_fifo_commit(dev_priv, sizeof(*cmd));
|
||||
}
|
||||
cmd->header.id = SVGA_3D_CMD_DESTROY_GB_MOB;
|
||||
cmd->header.size = sizeof(cmd->body);
|
||||
cmd->body.mobid = mob->id;
|
||||
vmw_fifo_commit(dev_priv, sizeof(*cmd));
|
||||
if (bo) {
|
||||
vmw_fence_single_bo(bo, NULL);
|
||||
ttm_bo_unreserve(bo);
|
||||
|
|
|
|||
|
|
@ -427,8 +427,7 @@ int vmw_dmabuf_init(struct vmw_private *dev_priv,
|
|||
INIT_LIST_HEAD(&vmw_bo->res_list);
|
||||
|
||||
ret = ttm_bo_init(bdev, &vmw_bo->base, size,
|
||||
(user) ? ttm_bo_type_device :
|
||||
ttm_bo_type_kernel, placement,
|
||||
ttm_bo_type_device, placement,
|
||||
0, interruptible,
|
||||
NULL, acc_size, NULL, bo_free);
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -538,7 +538,7 @@ int host1x_job_pin(struct host1x_job *job, struct device *dev)
|
|||
|
||||
g->base = job->gather_addr_phys[i];
|
||||
|
||||
for (j = 0; j < job->num_gathers; j++)
|
||||
for (j = i + 1; j < job->num_gathers; j++)
|
||||
if (job->gathers[j].bo == g->bo)
|
||||
job->gathers[j].handled = true;
|
||||
|
||||
|
|
|
|||
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Ссылка в новой задаче