staging: comedi: rtd520: use the comedi_device 'mmio' member
Use the new 'mmio' member in the comedi_device for the ioremap'ed base address of PCI bar 2. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten
Greg Kroah-Hartman
Родитель
9ebd1028cf
Коммит
c5930d66ac
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@ -373,7 +373,6 @@ static const struct rtd_boardinfo rtd520Boards[] = {
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struct rtd_private {
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/* memory mapped board structures */
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void __iomem *las0;
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void __iomem *las1;
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void __iomem *lcfg;
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@ -490,21 +489,19 @@ static unsigned short rtd_convert_chan_gain(struct comedi_device *dev,
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static void rtd_load_channelgain_list(struct comedi_device *dev,
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unsigned int n_chan, unsigned int *list)
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{
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struct rtd_private *devpriv = dev->private;
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if (n_chan > 1) { /* setup channel gain table */
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int ii;
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writel(0, devpriv->las0 + LAS0_CGT_CLEAR);
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writel(1, devpriv->las0 + LAS0_CGT_ENABLE);
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writel(0, dev->mmio + LAS0_CGT_CLEAR);
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writel(1, dev->mmio + LAS0_CGT_ENABLE);
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for (ii = 0; ii < n_chan; ii++) {
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writel(rtd_convert_chan_gain(dev, list[ii], ii),
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devpriv->las0 + LAS0_CGT_WRITE);
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dev->mmio + LAS0_CGT_WRITE);
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}
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} else { /* just use the channel gain latch */
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writel(0, devpriv->las0 + LAS0_CGT_ENABLE);
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writel(0, dev->mmio + LAS0_CGT_ENABLE);
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writel(rtd_convert_chan_gain(dev, list[0], 0),
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devpriv->las0 + LAS0_CGL_WRITE);
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dev->mmio + LAS0_CGL_WRITE);
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}
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}
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@ -512,23 +509,22 @@ static void rtd_load_channelgain_list(struct comedi_device *dev,
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empty status flag clears */
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static int rtd520_probe_fifo_depth(struct comedi_device *dev)
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{
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struct rtd_private *devpriv = dev->private;
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unsigned int chanspec = CR_PACK(0, 0, AREF_GROUND);
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unsigned i;
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static const unsigned limit = 0x2000;
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unsigned fifo_size = 0;
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writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
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writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
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rtd_load_channelgain_list(dev, 1, &chanspec);
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/* ADC conversion trigger source: SOFTWARE */
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writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
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writel(0, dev->mmio + LAS0_ADC_CONVERSION);
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/* convert samples */
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for (i = 0; i < limit; ++i) {
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unsigned fifo_status;
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/* trigger conversion */
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writew(0, devpriv->las0 + LAS0_ADC);
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writew(0, dev->mmio + LAS0_ADC);
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udelay(1);
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fifo_status = readl(devpriv->las0 + LAS0_ADC);
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fifo_status = readl(dev->mmio + LAS0_ADC);
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if ((fifo_status & FS_ADC_HEMPTY) == 0) {
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fifo_size = 2 * i;
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break;
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@ -538,7 +534,7 @@ static int rtd520_probe_fifo_depth(struct comedi_device *dev)
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dev_info(dev->class_dev, "failed to probe fifo size.\n");
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return -EIO;
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}
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writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
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writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
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if (fifo_size != 0x400 && fifo_size != 0x2000) {
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dev_info(dev->class_dev,
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"unexpected fifo size of %i, expected 1024 or 8192.\n",
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@ -553,10 +549,9 @@ static int rtd_ai_eoc(struct comedi_device *dev,
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struct comedi_insn *insn,
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unsigned long context)
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{
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struct rtd_private *devpriv = dev->private;
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unsigned int status;
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status = readl(devpriv->las0 + LAS0_ADC);
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status = readl(dev->mmio + LAS0_ADC);
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if (status & FS_ADC_NOT_EMPTY)
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return 0;
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return -EBUSY;
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@ -571,19 +566,19 @@ static int rtd_ai_rinsn(struct comedi_device *dev,
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int n;
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/* clear any old fifo data */
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writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
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writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
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/* write channel to multiplexer and clear channel gain table */
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rtd_load_channelgain_list(dev, 1, &insn->chanspec);
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/* ADC conversion trigger source: SOFTWARE */
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writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
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writel(0, dev->mmio + LAS0_ADC_CONVERSION);
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/* convert n samples */
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for (n = 0; n < insn->n; n++) {
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unsigned short d;
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/* trigger conversion */
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writew(0, devpriv->las0 + LAS0_ADC);
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writew(0, dev->mmio + LAS0_ADC);
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ret = comedi_timeout(dev, s, insn, rtd_ai_eoc, 0);
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if (ret)
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@ -645,7 +640,7 @@ static int ai_read_dregs(struct comedi_device *dev, struct comedi_subdevice *s)
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{
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struct rtd_private *devpriv = dev->private;
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while (readl(devpriv->las0 + LAS0_ADC) & FS_ADC_NOT_EMPTY) {
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while (readl(dev->mmio + LAS0_ADC) & FS_ADC_NOT_EMPTY) {
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unsigned short d = readw(devpriv->las1 + LAS1_ADC_FIFO);
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if (0 == devpriv->ai_count) { /* done */
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@ -685,12 +680,12 @@ static irqreturn_t rtd_interrupt(int irq, void *d)
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if (!dev->attached)
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return IRQ_NONE;
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fifo_status = readl(devpriv->las0 + LAS0_ADC);
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fifo_status = readl(dev->mmio + LAS0_ADC);
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/* check for FIFO full, this automatically halts the ADC! */
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if (!(fifo_status & FS_ADC_NOT_FULL)) /* 0 -> full */
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goto xfer_abort;
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status = readw(devpriv->las0 + LAS0_IT);
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status = readw(dev->mmio + LAS0_IT);
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/* if interrupt was not caused by our board, or handled above */
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if (0 == status)
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return IRQ_HANDLED;
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@ -725,30 +720,30 @@ static irqreturn_t rtd_interrupt(int irq, void *d)
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}
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}
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overrun = readl(devpriv->las0 + LAS0_OVERRUN) & 0xffff;
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overrun = readl(dev->mmio + LAS0_OVERRUN) & 0xffff;
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if (overrun)
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goto xfer_abort;
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/* clear the interrupt */
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writew(status, devpriv->las0 + LAS0_CLEAR);
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readw(devpriv->las0 + LAS0_CLEAR);
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writew(status, dev->mmio + LAS0_CLEAR);
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readw(dev->mmio + LAS0_CLEAR);
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return IRQ_HANDLED;
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xfer_abort:
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writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
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writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
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s->async->events |= COMEDI_CB_ERROR;
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devpriv->ai_count = 0; /* stop and don't transfer any more */
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/* fall into xfer_done */
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xfer_done:
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/* pacer stop source: SOFTWARE */
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writel(0, devpriv->las0 + LAS0_PACER_STOP);
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writel(0, devpriv->las0 + LAS0_PACER); /* stop pacer */
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writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
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writew(0, devpriv->las0 + LAS0_IT);
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writel(0, dev->mmio + LAS0_PACER_STOP);
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writel(0, dev->mmio + LAS0_PACER); /* stop pacer */
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writel(0, dev->mmio + LAS0_ADC_CONVERSION);
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writew(0, dev->mmio + LAS0_IT);
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if (devpriv->ai_count > 0) { /* there shouldn't be anything left */
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fifo_status = readl(devpriv->las0 + LAS0_ADC);
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fifo_status = readl(dev->mmio + LAS0_ADC);
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ai_read_dregs(dev, s); /* read anything left in FIFO */
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}
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@ -756,12 +751,12 @@ xfer_done:
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comedi_event(dev, s);
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/* clear the interrupt */
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status = readw(devpriv->las0 + LAS0_IT);
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writew(status, devpriv->las0 + LAS0_CLEAR);
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readw(devpriv->las0 + LAS0_CLEAR);
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status = readw(dev->mmio + LAS0_IT);
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writew(status, dev->mmio + LAS0_CLEAR);
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readw(dev->mmio + LAS0_CLEAR);
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fifo_status = readl(devpriv->las0 + LAS0_ADC);
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overrun = readl(devpriv->las0 + LAS0_OVERRUN) & 0xffff;
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fifo_status = readl(dev->mmio + LAS0_ADC);
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overrun = readl(dev->mmio + LAS0_OVERRUN) & 0xffff;
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return IRQ_HANDLED;
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}
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@ -931,12 +926,12 @@ static int rtd_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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/* stop anything currently running */
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/* pacer stop source: SOFTWARE */
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writel(0, devpriv->las0 + LAS0_PACER_STOP);
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writel(0, devpriv->las0 + LAS0_PACER); /* stop pacer */
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writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
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writew(0, devpriv->las0 + LAS0_IT);
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writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
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writel(0, devpriv->las0 + LAS0_OVERRUN);
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writel(0, dev->mmio + LAS0_PACER_STOP);
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writel(0, dev->mmio + LAS0_PACER); /* stop pacer */
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writel(0, dev->mmio + LAS0_ADC_CONVERSION);
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writew(0, dev->mmio + LAS0_IT);
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writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
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writel(0, dev->mmio + LAS0_OVERRUN);
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/* start configuration */
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/* load channel list and reset CGT */
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@ -945,18 +940,18 @@ static int rtd_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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/* setup the common case and override if needed */
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if (cmd->chanlist_len > 1) {
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/* pacer start source: SOFTWARE */
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writel(0, devpriv->las0 + LAS0_PACER_START);
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writel(0, dev->mmio + LAS0_PACER_START);
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/* burst trigger source: PACER */
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writel(1, devpriv->las0 + LAS0_BURST_START);
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writel(1, dev->mmio + LAS0_BURST_START);
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/* ADC conversion trigger source: BURST */
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writel(2, devpriv->las0 + LAS0_ADC_CONVERSION);
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writel(2, dev->mmio + LAS0_ADC_CONVERSION);
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} else { /* single channel */
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/* pacer start source: SOFTWARE */
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writel(0, devpriv->las0 + LAS0_PACER_START);
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writel(0, dev->mmio + LAS0_PACER_START);
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/* ADC conversion trigger source: PACER */
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writel(1, devpriv->las0 + LAS0_ADC_CONVERSION);
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writel(1, dev->mmio + LAS0_ADC_CONVERSION);
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}
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writel((devpriv->fifosz / 2 - 1) & 0xffff, devpriv->las0 + LAS0_ACNT);
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writel((devpriv->fifosz / 2 - 1) & 0xffff, dev->mmio + LAS0_ACNT);
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if (TRIG_TIMER == cmd->scan_begin_src) {
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/* scan_begin_arg is in nanoseconds */
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@ -993,16 +988,16 @@ static int rtd_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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} else {
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/* interrupt for each transfer */
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writel((devpriv->xfer_count - 1) & 0xffff,
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devpriv->las0 + LAS0_ACNT);
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dev->mmio + LAS0_ACNT);
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}
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} else { /* unknown timing, just use 1/2 FIFO */
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devpriv->xfer_count = 0;
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devpriv->flags &= ~SEND_EOS;
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}
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/* pacer clock source: INTERNAL 8MHz */
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writel(1, devpriv->las0 + LAS0_PACER_SELECT);
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writel(1, dev->mmio + LAS0_PACER_SELECT);
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/* just interrupt, don't stop */
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writel(1, devpriv->las0 + LAS0_ACNT_STOP_ENABLE);
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writel(1, dev->mmio + LAS0_ACNT_STOP_ENABLE);
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/* BUG??? these look like enumerated values, but they are bit fields */
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@ -1027,13 +1022,13 @@ static int rtd_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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timer = rtd_ns_to_timer(&cmd->scan_begin_arg,
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TRIG_ROUND_NEAREST);
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/* set PACER clock */
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writel(timer & 0xffffff, devpriv->las0 + LAS0_PCLK);
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writel(timer & 0xffffff, dev->mmio + LAS0_PCLK);
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break;
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case TRIG_EXT:
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/* pacer start source: EXTERNAL */
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writel(1, devpriv->las0 + LAS0_PACER_START);
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writel(1, dev->mmio + LAS0_PACER_START);
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break;
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}
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@ -1045,33 +1040,32 @@ static int rtd_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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timer = rtd_ns_to_timer(&cmd->convert_arg,
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TRIG_ROUND_NEAREST);
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/* setup BURST clock */
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writel(timer & 0x3ff, devpriv->las0 + LAS0_BCLK);
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writel(timer & 0x3ff, dev->mmio + LAS0_BCLK);
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}
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break;
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case TRIG_EXT: /* external */
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/* burst trigger source: EXTERNAL */
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writel(2, devpriv->las0 + LAS0_BURST_START);
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writel(2, dev->mmio + LAS0_BURST_START);
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break;
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}
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/* end configuration */
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/* This doesn't seem to work. There is no way to clear an interrupt
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that the priority controller has queued! */
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writew(~0, devpriv->las0 + LAS0_CLEAR);
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readw(devpriv->las0 + LAS0_CLEAR);
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writew(~0, dev->mmio + LAS0_CLEAR);
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readw(dev->mmio + LAS0_CLEAR);
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/* TODO: allow multiple interrupt sources */
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if (devpriv->xfer_count > 0) { /* transfer every N samples */
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writew(IRQM_ADC_ABOUT_CNT, devpriv->las0 + LAS0_IT);
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} else { /* 1/2 FIFO transfers */
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writew(IRQM_ADC_ABOUT_CNT, devpriv->las0 + LAS0_IT);
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}
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if (devpriv->xfer_count > 0) /* transfer every N samples */
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writew(IRQM_ADC_ABOUT_CNT, dev->mmio + LAS0_IT);
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else /* 1/2 FIFO transfers */
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writew(IRQM_ADC_ABOUT_CNT, dev->mmio + LAS0_IT);
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/* BUG: start_src is ASSUMED to be TRIG_NOW */
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/* BUG? it seems like things are running before the "start" */
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readl(devpriv->las0 + LAS0_PACER); /* start pacer */
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readl(dev->mmio + LAS0_PACER); /* start pacer */
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return 0;
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}
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@ -1085,13 +1079,13 @@ static int rtd_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
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u16 status;
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/* pacer stop source: SOFTWARE */
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writel(0, devpriv->las0 + LAS0_PACER_STOP);
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writel(0, devpriv->las0 + LAS0_PACER); /* stop pacer */
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writel(0, devpriv->las0 + LAS0_ADC_CONVERSION);
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writew(0, devpriv->las0 + LAS0_IT);
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writel(0, dev->mmio + LAS0_PACER_STOP);
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writel(0, dev->mmio + LAS0_PACER); /* stop pacer */
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writel(0, dev->mmio + LAS0_ADC_CONVERSION);
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writew(0, dev->mmio + LAS0_IT);
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devpriv->ai_count = 0; /* stop and don't transfer any more */
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status = readw(devpriv->las0 + LAS0_IT);
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overrun = readl(devpriv->las0 + LAS0_OVERRUN) & 0xffff;
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status = readw(dev->mmio + LAS0_IT);
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overrun = readl(dev->mmio + LAS0_OVERRUN) & 0xffff;
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return 0;
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}
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@ -1100,12 +1094,11 @@ static int rtd_ao_eoc(struct comedi_device *dev,
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struct comedi_insn *insn,
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unsigned long context)
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{
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struct rtd_private *devpriv = dev->private;
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unsigned int chan = CR_CHAN(insn->chanspec);
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unsigned int bit = (chan == 0) ? FS_DAC1_NOT_EMPTY : FS_DAC2_NOT_EMPTY;
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unsigned int status;
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status = readl(devpriv->las0 + LAS0_ADC);
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status = readl(dev->mmio + LAS0_ADC);
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if (status & bit)
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return 0;
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return -EBUSY;
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@ -1122,8 +1115,8 @@ static int rtd_ao_winsn(struct comedi_device *dev,
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int ret;
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/* Configure the output range (table index matches the range values) */
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writew(range & 7, devpriv->las0 +
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((chan == 0) ? LAS0_DAC1_CTRL : LAS0_DAC2_CTRL));
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writew(range & 7,
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dev->mmio + ((chan == 0) ? LAS0_DAC1_CTRL : LAS0_DAC2_CTRL));
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/* Writing a list of values to an AO channel is probably not
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* very useful, but that's how the interface is defined. */
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@ -1143,8 +1136,7 @@ static int rtd_ao_winsn(struct comedi_device *dev,
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/* a typical programming sequence */
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writew(val, devpriv->las1 +
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((chan == 0) ? LAS1_DAC1_FIFO : LAS1_DAC2_FIFO));
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writew(0, devpriv->las0 +
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((chan == 0) ? LAS0_DAC1 : LAS0_DAC2));
|
||||
writew(0, dev->mmio + ((chan == 0) ? LAS0_DAC1 : LAS0_DAC2));
|
||||
|
||||
devpriv->ao_readback[chan] = data[i];
|
||||
|
||||
|
|
@ -1179,12 +1171,10 @@ static int rtd_dio_insn_bits(struct comedi_device *dev,
|
|||
struct comedi_insn *insn,
|
||||
unsigned int *data)
|
||||
{
|
||||
struct rtd_private *devpriv = dev->private;
|
||||
|
||||
if (comedi_dio_update_state(s, data))
|
||||
writew(s->state & 0xff, devpriv->las0 + LAS0_DIO0);
|
||||
writew(s->state & 0xff, dev->mmio + LAS0_DIO0);
|
||||
|
||||
data[1] = readw(devpriv->las0 + LAS0_DIO0) & 0xff;
|
||||
data[1] = readw(dev->mmio + LAS0_DIO0) & 0xff;
|
||||
|
||||
return insn->n;
|
||||
}
|
||||
|
|
@ -1194,7 +1184,6 @@ static int rtd_dio_insn_config(struct comedi_device *dev,
|
|||
struct comedi_insn *insn,
|
||||
unsigned int *data)
|
||||
{
|
||||
struct rtd_private *devpriv = dev->private;
|
||||
int ret;
|
||||
|
||||
ret = comedi_dio_insn_config(dev, s, insn, data, 0);
|
||||
|
|
@ -1204,11 +1193,11 @@ static int rtd_dio_insn_config(struct comedi_device *dev,
|
|||
/* TODO support digital match interrupts and strobes */
|
||||
|
||||
/* set direction */
|
||||
writew(0x01, devpriv->las0 + LAS0_DIO_STATUS);
|
||||
writew(s->io_bits & 0xff, devpriv->las0 + LAS0_DIO0_CTRL);
|
||||
writew(0x01, dev->mmio + LAS0_DIO_STATUS);
|
||||
writew(s->io_bits & 0xff, dev->mmio + LAS0_DIO0_CTRL);
|
||||
|
||||
/* clear interrupts */
|
||||
writew(0x00, devpriv->las0 + LAS0_DIO_STATUS);
|
||||
writew(0x00, dev->mmio + LAS0_DIO_STATUS);
|
||||
|
||||
/* port1 can only be all input or all output */
|
||||
|
||||
|
|
@ -1221,12 +1210,12 @@ static void rtd_reset(struct comedi_device *dev)
|
|||
{
|
||||
struct rtd_private *devpriv = dev->private;
|
||||
|
||||
writel(0, devpriv->las0 + LAS0_BOARD_RESET);
|
||||
writel(0, dev->mmio + LAS0_BOARD_RESET);
|
||||
udelay(100); /* needed? */
|
||||
writel(0, devpriv->lcfg + PLX_INTRCS_REG);
|
||||
writew(0, devpriv->las0 + LAS0_IT);
|
||||
writew(~0, devpriv->las0 + LAS0_CLEAR);
|
||||
readw(devpriv->las0 + LAS0_CLEAR);
|
||||
writew(0, dev->mmio + LAS0_IT);
|
||||
writew(~0, dev->mmio + LAS0_CLEAR);
|
||||
readw(dev->mmio + LAS0_CLEAR);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -1235,21 +1224,19 @@ static void rtd_reset(struct comedi_device *dev)
|
|||
*/
|
||||
static void rtd_init_board(struct comedi_device *dev)
|
||||
{
|
||||
struct rtd_private *devpriv = dev->private;
|
||||
|
||||
rtd_reset(dev);
|
||||
|
||||
writel(0, devpriv->las0 + LAS0_OVERRUN);
|
||||
writel(0, devpriv->las0 + LAS0_CGT_CLEAR);
|
||||
writel(0, devpriv->las0 + LAS0_ADC_FIFO_CLEAR);
|
||||
writel(0, devpriv->las0 + LAS0_DAC1_RESET);
|
||||
writel(0, devpriv->las0 + LAS0_DAC2_RESET);
|
||||
writel(0, dev->mmio + LAS0_OVERRUN);
|
||||
writel(0, dev->mmio + LAS0_CGT_CLEAR);
|
||||
writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR);
|
||||
writel(0, dev->mmio + LAS0_DAC1_RESET);
|
||||
writel(0, dev->mmio + LAS0_DAC2_RESET);
|
||||
/* clear digital IO fifo */
|
||||
writew(0, devpriv->las0 + LAS0_DIO_STATUS);
|
||||
writeb((0 << 6) | 0x30, devpriv->las0 + LAS0_UTC_CTRL);
|
||||
writeb((1 << 6) | 0x30, devpriv->las0 + LAS0_UTC_CTRL);
|
||||
writeb((2 << 6) | 0x30, devpriv->las0 + LAS0_UTC_CTRL);
|
||||
writeb((3 << 6) | 0x00, devpriv->las0 + LAS0_UTC_CTRL);
|
||||
writew(0, dev->mmio + LAS0_DIO_STATUS);
|
||||
writeb((0 << 6) | 0x30, dev->mmio + LAS0_UTC_CTRL);
|
||||
writeb((1 << 6) | 0x30, dev->mmio + LAS0_UTC_CTRL);
|
||||
writeb((2 << 6) | 0x30, dev->mmio + LAS0_UTC_CTRL);
|
||||
writeb((3 << 6) | 0x00, dev->mmio + LAS0_UTC_CTRL);
|
||||
/* TODO: set user out source ??? */
|
||||
}
|
||||
|
||||
|
|
@ -1292,10 +1279,10 @@ static int rtd_auto_attach(struct comedi_device *dev,
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
devpriv->las0 = pci_ioremap_bar(pcidev, 2);
|
||||
dev->mmio = pci_ioremap_bar(pcidev, 2);
|
||||
devpriv->las1 = pci_ioremap_bar(pcidev, 3);
|
||||
devpriv->lcfg = pci_ioremap_bar(pcidev, 0);
|
||||
if (!devpriv->las0 || !devpriv->las1 || !devpriv->lcfg)
|
||||
if (!dev->mmio || !devpriv->las1 || !devpriv->lcfg)
|
||||
return -ENOMEM;
|
||||
|
||||
rtd_pci_latency_quirk(dev, pcidev);
|
||||
|
|
@ -1375,7 +1362,7 @@ static void rtd_detach(struct comedi_device *dev)
|
|||
|
||||
if (devpriv) {
|
||||
/* Shut down any board ops by resetting it */
|
||||
if (devpriv->las0 && devpriv->lcfg)
|
||||
if (dev->mmio && devpriv->lcfg)
|
||||
rtd_reset(dev);
|
||||
if (dev->irq) {
|
||||
writel(readl(devpriv->lcfg + PLX_INTRCS_REG) &
|
||||
|
|
@ -1383,8 +1370,8 @@ static void rtd_detach(struct comedi_device *dev)
|
|||
devpriv->lcfg + PLX_INTRCS_REG);
|
||||
free_irq(dev->irq, dev);
|
||||
}
|
||||
if (devpriv->las0)
|
||||
iounmap(devpriv->las0);
|
||||
if (dev->mmio)
|
||||
iounmap(dev->mmio);
|
||||
if (devpriv->las1)
|
||||
iounmap(devpriv->las1);
|
||||
if (devpriv->lcfg)
|
||||
|
|
|
|||
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