x86, ioapic: Split up setup_ioapic_entry()
Ingo pointed out that setup_ioapic_entry() is way too big now. Split the intr-remap code out into setup_ir_ioapic_entry(). Also pass struct io_apic_irq_attr * instead of 5 parameters in those two functions. At last in setup_ir_ioapic_entry() we don't need to panic. Signed-off-by: Yinghai Lu <yinghai@kernel.org> Cc: Naga Chumbalkar <nagananda.chumbalkar@hp.com> Cc: Suresh Siddha <suresh.b.siddha@intel.com> Link: http://lkml.kernel.org/r/4E9542BB.4070807@oracle.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Yinghai Lu
Ingo Molnar
Родитель
e4aff81182
Коммит
c5b4712c3f
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@ -1255,72 +1255,95 @@ static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
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fasteoi ? "fasteoi" : "edge");
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}
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static int setup_ioapic_entry(int apic_id, int irq,
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struct IO_APIC_route_entry *entry,
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unsigned int destination, int trigger,
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int polarity, int vector, int pin)
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static int setup_ir_ioapic_entry(int irq,
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struct IR_IO_APIC_route_entry *entry,
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unsigned int destination, int vector,
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struct io_apic_irq_attr *attr)
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{
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/*
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* add it to the IO-APIC irq-routing table:
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*/
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memset(entry,0,sizeof(*entry));
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int index;
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struct irte irte;
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int apic_id = mpc_ioapic_id(attr->ioapic);
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struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
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if (intr_remapping_enabled) {
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struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
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struct irte irte;
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struct IR_IO_APIC_route_entry *ir_entry =
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(struct IR_IO_APIC_route_entry *) entry;
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int index;
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if (!iommu)
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panic("No mapping iommu for ioapic %d\n", apic_id);
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index = alloc_irte(iommu, irq, 1);
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if (index < 0)
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panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
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prepare_irte(&irte, vector, destination);
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/* Set source-id of interrupt request */
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set_ioapic_sid(&irte, apic_id);
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modify_irte(irq, &irte);
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ir_entry->index2 = (index >> 15) & 0x1;
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ir_entry->zero = 0;
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ir_entry->format = 1;
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ir_entry->index = (index & 0x7fff);
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/*
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* IO-APIC RTE will be configured with virtual vector.
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* irq handler will do the explicit EOI to the io-apic.
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*/
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ir_entry->vector = pin;
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apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: "
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"Set IRTE entry (P:%d FPD:%d Dst_Mode:%d "
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"Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X "
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"Avail:%X Vector:%02X Dest:%08X "
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"SID:%04X SQ:%X SVT:%X)\n",
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apic_id, irte.present, irte.fpd, irte.dst_mode,
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irte.redir_hint, irte.trigger_mode, irte.dlvry_mode,
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irte.avail, irte.vector, irte.dest_id,
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irte.sid, irte.sq, irte.svt);
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} else {
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entry->delivery_mode = apic->irq_delivery_mode;
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entry->dest_mode = apic->irq_dest_mode;
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entry->dest = destination;
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entry->vector = vector;
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if (!iommu) {
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pr_warn("No mapping iommu for ioapic %d\n", apic_id);
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return -ENODEV;
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}
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entry->mask = 0; /* enable IRQ */
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entry->trigger = trigger;
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entry->polarity = polarity;
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index = alloc_irte(iommu, irq, 1);
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if (index < 0) {
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pr_warn("Failed to allocate IRTE for ioapic %d\n", apic_id);
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return -ENOMEM;
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}
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prepare_irte(&irte, vector, destination);
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/* Set source-id of interrupt request */
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set_ioapic_sid(&irte, apic_id);
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modify_irte(irq, &irte);
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apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: "
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"Set IRTE entry (P:%d FPD:%d Dst_Mode:%d "
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"Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X "
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"Avail:%X Vector:%02X Dest:%08X "
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"SID:%04X SQ:%X SVT:%X)\n",
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apic_id, irte.present, irte.fpd, irte.dst_mode,
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irte.redir_hint, irte.trigger_mode, irte.dlvry_mode,
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irte.avail, irte.vector, irte.dest_id,
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irte.sid, irte.sq, irte.svt);
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memset(entry, 0, sizeof(*entry));
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entry->index2 = (index >> 15) & 0x1;
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entry->zero = 0;
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entry->format = 1;
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entry->index = (index & 0x7fff);
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/*
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* IO-APIC RTE will be configured with virtual vector.
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* irq handler will do the explicit EOI to the io-apic.
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*/
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entry->vector = attr->ioapic_pin;
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entry->mask = 0; /* enable IRQ */
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entry->trigger = attr->trigger;
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entry->polarity = attr->polarity;
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/* Mask level triggered irqs.
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* Use IRQ_DELAYED_DISABLE for edge triggered irqs.
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*/
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if (trigger)
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if (attr->trigger)
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entry->mask = 1;
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return 0;
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}
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static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
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unsigned int destination, int vector,
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struct io_apic_irq_attr *attr)
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{
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if (intr_remapping_enabled)
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return setup_ir_ioapic_entry(irq,
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(struct IR_IO_APIC_route_entry *)entry,
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destination, vector, attr);
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memset(entry, 0, sizeof(*entry));
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entry->delivery_mode = apic->irq_delivery_mode;
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entry->dest_mode = apic->irq_dest_mode;
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entry->dest = destination;
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entry->vector = vector;
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entry->mask = 0; /* enable IRQ */
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entry->trigger = attr->trigger;
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entry->polarity = attr->polarity;
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/*
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* Mask level triggered irqs.
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* Use IRQ_DELAYED_DISABLE for edge triggered irqs.
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*/
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if (attr->trigger)
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entry->mask = 1;
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return 0;
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}
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@ -1351,13 +1374,11 @@ static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg,
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attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin,
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cfg->vector, irq, attr->trigger, attr->polarity, dest);
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if (setup_ioapic_entry(mpc_ioapic_id(attr->ioapic), irq, &entry,
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dest, attr->trigger, attr->polarity, cfg->vector,
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attr->ioapic_pin)) {
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printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
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mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
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if (setup_ioapic_entry(irq, &entry, dest, cfg->vector, attr)) {
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pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n",
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mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
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__clear_irq_vector(irq, cfg);
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return;
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}
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