PCI: thunder-pem: Add support for cn81xx and cn83xx SoCs
The pci-thunder-pem driver was initially developed for cn88xx SoCs. The cn81xx and cn83xx members of the same family of SoCs have a slightly different configuration of interrupt resources in the PEM hardware, which prevents the INTA legacy interrupt source from functioning with the current driver. There are two fixes required: 1) Don't fixup the PME interrupt on the newer SoCs as it already has the proper value. 2) Report MSI-X Capability Table Size of 2 for the newer SoCs, so the core MSI-X code doesn't inadvertently clobber the INTA machinery that happens to reside immediately following the table. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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@ -36,7 +36,7 @@ struct thunder_pem_pci {
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static int thunder_pem_bridge_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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u64 read_val;
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u64 read_val, tmp_val;
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struct pci_config_window *cfg = bus->sysdata;
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struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv;
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@ -65,13 +65,28 @@ static int thunder_pem_bridge_read(struct pci_bus *bus, unsigned int devfn,
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read_val |= 0x00007000; /* Skip MSI CAP */
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break;
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case 0x70: /* Express Cap */
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/* PME interrupt on vector 2*/
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read_val |= (2u << 25);
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/*
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* Change PME interrupt to vector 2 on T88 where it
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* reads as 0, else leave it alone.
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*/
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if (!(read_val & (0x1f << 25)))
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read_val |= (2u << 25);
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break;
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case 0xb0: /* MSI-X Cap */
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/* TableSize=4, Next Cap is EA */
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/* TableSize=2 or 4, Next Cap is EA */
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read_val &= 0xc00000ff;
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read_val |= 0x0003bc00;
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/*
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* If Express Cap(0x70) raw PME vector reads as 0 we are on
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* T88 and TableSize is reported as 4, else TableSize
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* is 2.
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*/
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writeq(0x70, pem_pci->pem_reg_base + PEM_CFG_RD);
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tmp_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
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tmp_val >>= 32;
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if (!(tmp_val & (0x1f << 25)))
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read_val |= 0x0003bc00;
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else
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read_val |= 0x0001bc00;
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break;
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case 0xb4:
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/* Table offset=0, BIR=0 */
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