Merge branch 'pci/enumeration' into next
* pci/enumeration:
PCI: Warn periodically while waiting for non-CRS ("device ready") status
PCI: Wait up to 60 seconds for device to become ready after FLR
PCI: Factor out pci_bus_wait_crs()
PCI: Add pci_bus_crs_vendor_id() to detect CRS response data
PCI: Always check for non-CRS response before timeout
PCI: Avoid race while enabling upstream bridges
PCI: Mark Broadcom HT2100 Root Port Extended Tags as broken
This commit is contained in:
Bjorn Helgaas
Коммит
c5efc22095
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@ -52,6 +52,7 @@ static void pci_pme_list_scan(struct work_struct *work);
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static LIST_HEAD(pci_pme_list);
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static DEFINE_MUTEX(pci_pme_list_mutex);
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static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
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static DEFINE_MUTEX(pci_bridge_mutex);
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struct pci_pme_device {
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struct list_head list;
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@ -1348,10 +1349,16 @@ static void pci_enable_bridge(struct pci_dev *dev)
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if (bridge)
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pci_enable_bridge(bridge);
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/*
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* Hold pci_bridge_mutex to prevent a race when enabling two
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* devices below the bridge simultaneously. The race may cause a
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* PCI_COMMAND_MEMORY update to be lost (see changelog).
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*/
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mutex_lock(&pci_bridge_mutex);
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if (pci_is_enabled(dev)) {
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if (!dev->is_busmaster)
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pci_set_master(dev);
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return;
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goto end;
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}
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retval = pci_enable_device(dev);
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@ -1359,6 +1366,8 @@ static void pci_enable_bridge(struct pci_dev *dev)
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dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
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retval);
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pci_set_master(dev);
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end:
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mutex_unlock(&pci_bridge_mutex);
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}
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static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
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@ -1383,7 +1392,7 @@ static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
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return 0; /* already enabled */
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bridge = pci_upstream_bridge(dev);
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if (bridge)
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if (bridge && !pci_is_enabled(bridge))
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pci_enable_bridge(bridge);
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/* only skip sriov related */
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@ -3811,27 +3820,49 @@ int pci_wait_for_pending_transaction(struct pci_dev *dev)
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}
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EXPORT_SYMBOL(pci_wait_for_pending_transaction);
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/*
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* We should only need to wait 100ms after FLR, but some devices take longer.
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* Wait for up to 1000ms for config space to return something other than -1.
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* Intel IGD requires this when an LCD panel is attached. We read the 2nd
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* dword because VFs don't implement the 1st dword.
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*/
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static void pci_flr_wait(struct pci_dev *dev)
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{
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int i = 0;
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int delay = 1, timeout = 60000;
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u32 id;
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do {
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msleep(100);
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pci_read_config_dword(dev, PCI_COMMAND, &id);
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} while (i++ < 10 && id == ~0);
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/*
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* Per PCIe r3.1, sec 6.6.2, a device must complete an FLR within
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* 100ms, but may silently discard requests while the FLR is in
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* progress. Wait 100ms before trying to access the device.
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*/
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msleep(100);
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if (id == ~0)
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dev_warn(&dev->dev, "Failed to return from FLR\n");
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else if (i > 1)
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dev_info(&dev->dev, "Required additional %dms to return from FLR\n",
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(i - 1) * 100);
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/*
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* After 100ms, the device should not silently discard config
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* requests, but it may still indicate that it needs more time by
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* responding to them with CRS completions. The Root Port will
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* generally synthesize ~0 data to complete the read (except when
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* CRS SV is enabled and the read was for the Vendor ID; in that
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* case it synthesizes 0x0001 data).
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*
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* Wait for the device to return a non-CRS completion. Read the
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* Command register instead of Vendor ID so we don't have to
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* contend with the CRS SV value.
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*/
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pci_read_config_dword(dev, PCI_COMMAND, &id);
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while (id == ~0) {
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if (delay > timeout) {
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dev_warn(&dev->dev, "not ready %dms after FLR; giving up\n",
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100 + delay - 1);
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return;
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}
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if (delay > 1000)
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dev_info(&dev->dev, "not ready %dms after FLR; waiting\n",
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100 + delay - 1);
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msleep(delay);
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delay *= 2;
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pci_read_config_dword(dev, PCI_COMMAND, &id);
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}
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if (delay > 1000)
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dev_info(&dev->dev, "ready %dms after FLR\n", 100 + delay - 1);
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}
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/**
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@ -235,6 +235,7 @@ enum pci_bar_type {
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pci_bar_mem64, /* A 64-bit memory BAR */
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};
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int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
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bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
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int crs_timeout);
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int pci_setup_device(struct pci_dev *dev);
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@ -1745,21 +1745,50 @@ static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
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*/
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}
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static void pci_configure_extended_tags(struct pci_dev *dev)
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int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
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{
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u32 dev_cap;
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struct pci_host_bridge *host;
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u32 cap;
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u16 ctl;
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int ret;
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if (!pci_is_pcie(dev))
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return;
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return 0;
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ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &dev_cap);
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ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
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if (ret)
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return;
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return 0;
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if (dev_cap & PCI_EXP_DEVCAP_EXT_TAG)
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if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))
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return 0;
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ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
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if (ret)
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return 0;
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host = pci_find_host_bridge(dev->bus);
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if (!host)
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return 0;
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/*
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* If some device in the hierarchy doesn't handle Extended Tags
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* correctly, make sure they're disabled.
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*/
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if (host->no_ext_tags) {
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if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
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dev_info(&dev->dev, "disabling Extended Tags\n");
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pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
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PCI_EXP_DEVCTL_EXT_TAG);
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}
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return 0;
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}
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if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
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dev_info(&dev->dev, "enabling Extended Tags\n");
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pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
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PCI_EXP_DEVCTL_EXT_TAG);
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}
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return 0;
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}
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static void pci_configure_device(struct pci_dev *dev)
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@ -1768,7 +1797,7 @@ static void pci_configure_device(struct pci_dev *dev)
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int ret;
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pci_configure_mps(dev);
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pci_configure_extended_tags(dev);
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pci_configure_extended_tags(dev, NULL);
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memset(&hpp, 0, sizeof(hpp));
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ret = pci_get_hp_params(dev, &hpp);
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@ -1824,11 +1853,58 @@ struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
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}
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EXPORT_SYMBOL(pci_alloc_dev);
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bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
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int crs_timeout)
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static bool pci_bus_crs_vendor_id(u32 l)
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{
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return (l & 0xffff) == 0x0001;
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}
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static bool pci_bus_wait_crs(struct pci_bus *bus, int devfn, u32 *l,
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int timeout)
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{
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int delay = 1;
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if (!pci_bus_crs_vendor_id(*l))
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return true; /* not a CRS completion */
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if (!timeout)
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return false; /* CRS, but caller doesn't want to wait */
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/*
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* We got the reserved Vendor ID that indicates a completion with
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* Configuration Request Retry Status (CRS). Retry until we get a
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* valid Vendor ID or we time out.
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*/
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while (pci_bus_crs_vendor_id(*l)) {
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if (delay > timeout) {
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pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
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pci_domain_nr(bus), bus->number,
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PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
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return false;
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}
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if (delay >= 1000)
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pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
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pci_domain_nr(bus), bus->number,
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PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
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msleep(delay);
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delay *= 2;
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if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
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return false;
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}
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if (delay >= 1000)
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pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
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pci_domain_nr(bus), bus->number,
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PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
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return true;
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}
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bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
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int timeout)
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{
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if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
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return false;
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@ -1837,28 +1913,8 @@ bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
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*l == 0x0000ffff || *l == 0xffff0000)
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return false;
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/*
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* Configuration Request Retry Status. Some root ports return the
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* actual device ID instead of the synthetic ID (0xFFFF) required
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* by the PCIe spec. Ignore the device ID and only check for
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* (vendor id == 1).
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*/
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while ((*l & 0xffff) == 0x0001) {
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if (!crs_timeout)
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return false;
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msleep(delay);
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delay *= 2;
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if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
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return false;
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/* Card hasn't responded in 60 seconds? Must be stuck. */
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if (delay > crs_timeout) {
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printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
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pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
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PCI_FUNC(devfn));
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return false;
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}
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}
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if (pci_bus_crs_vendor_id(*l))
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return pci_bus_wait_crs(bus, devfn, l, timeout);
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return true;
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}
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@ -4664,3 +4664,19 @@ static void quirk_intel_no_flr(struct pci_dev *dev)
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr);
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static void quirk_no_ext_tags(struct pci_dev *pdev)
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{
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struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
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if (!bridge)
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return;
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bridge->no_ext_tags = 1;
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dev_info(&pdev->dev, "disabling Extended Tags (this device can't handle them)\n");
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pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
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@ -473,6 +473,7 @@ struct pci_host_bridge {
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void *release_data;
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struct msi_controller *msi;
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unsigned int ignore_reset_delay:1; /* for entire hierarchy */
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unsigned int no_ext_tags:1; /* no Extended Tags */
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/* Resource alignment requirements */
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resource_size_t (*align_resource)(struct pci_dev *dev,
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const struct resource *res,
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