[media] c8sectpfe: STiH407/10 Linux DVB demux support
This patch adds support for the c8sectpfe input HW found on STiH407/410 SoC's. It currently supports the TS input block, memdma engine and hw PID filtering blocks of the C8SECTPFE subsystem. The driver creates one LinuxDVB adapter, and a demux/dvr/frontend set of devices for each tsin channel which is specificed in the DT. It has been tested with multiple tsin channels tuned, locked, and grabbing TS simultaneously. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
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Peter Griffin
Mauro Carvalho Chehab
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/*
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* c8sectpfe-core.h - C8SECTPFE STi DVB driver
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*
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* Copyright (c) STMicroelectronics 2015
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*
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* Author:Peter Bennett <peter.bennett@st.com>
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* Peter Griffin <peter.griffin@linaro.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#ifndef _C8SECTPFE_CORE_H_
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#define _C8SECTPFE_CORE_H_
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#define C8SECTPFEI_MAXCHANNEL 16
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#define C8SECTPFEI_MAXADAPTER 3
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#define C8SECTPFE_MAX_TSIN_CHAN 8
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struct channel_info {
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int tsin_id;
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bool invert_ts_clk;
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bool serial_not_parallel;
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bool async_not_sync;
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int i2c;
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int dvb_card;
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int rst_gpio;
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struct i2c_adapter *i2c_adapter;
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struct i2c_adapter *tuner_i2c;
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struct i2c_adapter *lnb_i2c;
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struct i2c_client *i2c_client;
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struct dvb_frontend *frontend;
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struct pinctrl_state *pstate;
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int demux_mapping;
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int active;
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void *back_buffer_start;
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void *back_buffer_aligned;
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dma_addr_t back_buffer_busaddr;
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void *pid_buffer_start;
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void *pid_buffer_aligned;
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dma_addr_t pid_buffer_busaddr;
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unsigned long fifo;
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struct completion idle_completion;
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struct tasklet_struct tsklet;
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struct c8sectpfei *fei;
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void __iomem *irec;
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};
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struct c8sectpfe_hw {
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int num_ib;
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int num_mib;
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int num_swts;
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int num_tsout;
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int num_ccsc;
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int num_ram;
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int num_tp;
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};
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struct c8sectpfei {
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struct device *dev;
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struct pinctrl *pinctrl;
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struct dentry *root;
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struct debugfs_regset32 *regset;
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struct completion fw_ack;
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atomic_t fw_loaded;
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int tsin_count;
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struct c8sectpfe_hw hw_stats;
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struct c8sectpfe *c8sectpfe[C8SECTPFEI_MAXADAPTER];
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int mapping[C8SECTPFEI_MAXCHANNEL];
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struct mutex lock;
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struct timer_list timer; /* timer interrupts for outputs */
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void __iomem *io;
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void __iomem *sram;
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unsigned long sram_size;
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struct channel_info *channel_data[C8SECTPFE_MAX_TSIN_CHAN];
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struct clk *c8sectpfeclk;
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int nima_rst_gpio;
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int nimb_rst_gpio;
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int idle_irq;
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int error_irq;
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int global_feed_count;
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};
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/* C8SECTPFE SYS Regs list */
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#define SYS_INPUT_ERR_STATUS 0x0
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#define SYS_OTHER_ERR_STATUS 0x8
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#define SYS_INPUT_ERR_MASK 0x10
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#define SYS_OTHER_ERR_MASK 0x18
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#define SYS_DMA_ROUTE 0x20
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#define SYS_INPUT_CLKEN 0x30
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#define IBENABLE_MASK 0x7F
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#define SYS_OTHER_CLKEN 0x38
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#define TSDMAENABLE BIT(1)
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#define MEMDMAENABLE BIT(0)
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#define SYS_CFG_NUM_IB 0x200
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#define SYS_CFG_NUM_MIB 0x204
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#define SYS_CFG_NUM_SWTS 0x208
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#define SYS_CFG_NUM_TSOUT 0x20C
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#define SYS_CFG_NUM_CCSC 0x210
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#define SYS_CFG_NUM_RAM 0x214
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#define SYS_CFG_NUM_TP 0x218
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/* Input Block Regs */
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#define C8SECTPFE_INPUTBLK_OFFSET 0x1000
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#define C8SECTPFE_CHANNEL_OFFSET(x) ((x*0x40) + C8SECTPFE_INPUTBLK_OFFSET)
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#define C8SECTPFE_IB_IP_FMT_CFG(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x00)
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#define C8SECTPFE_IGNORE_ERR_AT_SOP BIT(7)
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#define C8SECTPFE_IGNORE_ERR_IN_PKT BIT(6)
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#define C8SECTPFE_IGNORE_ERR_IN_BYTE BIT(5)
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#define C8SECTPFE_INVERT_TSCLK BIT(4)
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#define C8SECTPFE_ALIGN_BYTE_SOP BIT(3)
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#define C8SECTPFE_ASYNC_NOT_SYNC BIT(2)
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#define C8SECTPFE_BYTE_ENDIANNESS_MSB BIT(1)
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#define C8SECTPFE_SERIAL_NOT_PARALLEL BIT(0)
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#define C8SECTPFE_IB_SYNCLCKDRP_CFG(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x04)
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#define C8SECTPFE_SYNC(x) (x & 0xf)
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#define C8SECTPFE_DROP(x) ((x<<4) & 0xf)
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#define C8SECTPFE_TOKEN(x) ((x<<8) & 0xff00)
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#define C8SECTPFE_SLDENDIANNESS BIT(16)
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#define C8SECTPFE_IB_TAGBYTES_CFG(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x08)
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#define C8SECTPFE_TAG_HEADER(x) (x << 16)
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#define C8SECTPFE_TAG_COUNTER(x) ((x<<1) & 0x7fff)
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#define C8SECTPFE_TAG_ENABLE BIT(0)
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#define C8SECTPFE_IB_PID_SET(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x0C)
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#define C8SECTPFE_PID_OFFSET(x) (x & 0x3f)
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#define C8SECTPFE_PID_NUMBITS(x) ((x << 6) & 0xfff)
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#define C8SECTPFE_PID_ENABLE BIT(31)
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#define C8SECTPFE_IB_PKT_LEN(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x10)
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#define C8SECTPFE_IB_BUFF_STRT(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x14)
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#define C8SECTPFE_IB_BUFF_END(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x18)
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#define C8SECTPFE_IB_READ_PNT(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x1C)
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#define C8SECTPFE_IB_WRT_PNT(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x20)
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#define C8SECTPFE_IB_PRI_THRLD(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x24)
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#define C8SECTPFE_PRI_VALUE(x) (x & 0x7fffff)
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#define C8SECTPFE_PRI_LOWPRI(x) ((x & 0xf) << 24)
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#define C8SECTPFE_PRI_HIGHPRI(x) ((x & 0xf) << 28)
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#define C8SECTPFE_IB_STAT(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x28)
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#define C8SECTPFE_STAT_FIFO_OVERFLOW(x) (x & 0x1)
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#define C8SECTPFE_STAT_BUFFER_OVERFLOW(x) (x & 0x2)
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#define C8SECTPFE_STAT_OUTOFORDERRP(x) (x & 0x4)
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#define C8SECTPFE_STAT_PID_OVERFLOW(x) (x & 0x8)
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#define C8SECTPFE_STAT_PKT_OVERFLOW(x) (x & 0x10)
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#define C8SECTPFE_STAT_ERROR_PACKETS(x) ((x >> 8) & 0xf)
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#define C8SECTPFE_STAT_SHORT_PACKETS(x) ((x >> 12) & 0xf)
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#define C8SECTPFE_IB_MASK(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x2C)
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#define C8SECTPFE_MASK_FIFO_OVERFLOW BIT(0)
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#define C8SECTPFE_MASK_BUFFER_OVERFLOW BIT(1)
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#define C8SECTPFE_MASK_OUTOFORDERRP(x) BIT(2)
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#define C8SECTPFE_MASK_PID_OVERFLOW(x) BIT(3)
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#define C8SECTPFE_MASK_PKT_OVERFLOW(x) BIT(4)
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#define C8SECTPFE_MASK_ERROR_PACKETS(x) ((x & 0xf) << 8)
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#define C8SECTPFE_MASK_SHORT_PACKETS(x) ((x & 0xf) >> 12)
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#define C8SECTPFE_IB_SYS(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x30)
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#define C8SECTPFE_SYS_RESET BIT(1)
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#define C8SECTPFE_SYS_ENABLE BIT(0)
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/*
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* Ponter record data structure required for each input block
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* see Table 82 on page 167 of functional specification.
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*/
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#define DMA_PRDS_MEMBASE 0x0 /* Internal sram base address */
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#define DMA_PRDS_MEMTOP 0x4 /* Internal sram top address */
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/*
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* TS packet size, including tag bytes added by input block,
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* rounded up to the next multiple of 8 bytes. The packet size,
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* including any tagging bytes and rounded up to the nearest
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* multiple of 8 bytes must be less than 255 bytes.
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*/
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#define DMA_PRDS_PKTSIZE 0x8
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#define DMA_PRDS_TPENABLE 0xc
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#define TP0_OFFSET 0x10
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#define DMA_PRDS_BUSBASE_TP(x) ((0x10*x) + TP0_OFFSET)
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#define DMA_PRDS_BUSTOP_TP(x) ((0x10*x) + TP0_OFFSET + 0x4)
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#define DMA_PRDS_BUSWP_TP(x) ((0x10*x) + TP0_OFFSET + 0x8)
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#define DMA_PRDS_BUSRP_TP(x) ((0x10*x) + TP0_OFFSET + 0xc)
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#define DMA_PRDS_SIZE (0x20)
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#define DMA_MEMDMA_OFFSET 0x4000
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#define DMA_IMEM_OFFSET 0x0
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#define DMA_DMEM_OFFSET 0x4000
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#define DMA_CPU 0x8000
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#define DMA_PER_OFFSET 0xb000
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#define DMA_MEMDMA_DMEM (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET)
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#define DMA_MEMDMA_IMEM (DMA_MEMDMA_OFFSET + DMA_IMEM_OFFSET)
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/* XP70 Slim core regs */
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#define DMA_CPU_ID (DMA_MEMDMA_OFFSET + DMA_CPU + 0x0)
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#define DMA_CPU_VCR (DMA_MEMDMA_OFFSET + DMA_CPU + 0x4)
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#define DMA_CPU_RUN (DMA_MEMDMA_OFFSET + DMA_CPU + 0x8)
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#define DMA_CPU_CLOCKGATE (DMA_MEMDMA_OFFSET + DMA_CPU + 0xc)
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#define DMA_CPU_PC (DMA_MEMDMA_OFFSET + DMA_CPU + 0x20)
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/* Enable Interrupt for a IB */
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#define DMA_PER_TPn_DREQ_MASK (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xd00)
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/* Ack interrupt by setting corresponding bit */
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#define DMA_PER_TPn_DACK_SET (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xd80)
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#define DMA_PER_TPn_DREQ (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xe00)
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#define DMA_PER_TPn_DACK (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xe80)
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#define DMA_PER_DREQ_MODE (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xf80)
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#define DMA_PER_STBUS_SYNC (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xf88)
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#define DMA_PER_STBUS_ACCESS (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xf8c)
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#define DMA_PER_STBUS_ADDRESS (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xf90)
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#define DMA_PER_IDLE_INT (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfa8)
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#define DMA_PER_PRIORITY (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfac)
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#define DMA_PER_MAX_OPCODE (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfb0)
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#define DMA_PER_MAX_CHUNK (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfb4)
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#define DMA_PER_PAGE_SIZE (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfbc)
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#define DMA_PER_MBOX_STATUS (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfc0)
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#define DMA_PER_MBOX_SET (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfc8)
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#define DMA_PER_MBOX_CLEAR (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfd0)
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#define DMA_PER_MBOX_MASK (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfd8)
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#define DMA_PER_INJECT_PKT_SRC (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfe0)
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#define DMA_PER_INJECT_PKT_DEST (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfe4)
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#define DMA_PER_INJECT_PKT_ADDR (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfe8)
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#define DMA_PER_INJECT_PKT (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfec)
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#define DMA_PER_PAT_PTR_INIT (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xff0)
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#define DMA_PER_PAT_PTR (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xff4)
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#define DMA_PER_SLEEP_MASK (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xff8)
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#define DMA_PER_SLEEP_COUNTER (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xffc)
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/* #define DMA_RF_CPUREGn DMA_RFBASEADDR n=0 to 15) slim regsa */
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/* The following are from DMA_DMEM_BaseAddress */
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#define DMA_FIRMWARE_VERSION (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET + 0x0)
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#define DMA_PTRREC_BASE (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET + 0x4)
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#define DMA_PTRREC_INPUT_OFFSET (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET + 0x8)
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#define DMA_ERRREC_BASE (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET + 0xc)
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#define DMA_ERROR_RECORD(n) ((n*4) + DMA_ERRREC_BASE + 0x4)
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#define DMA_IDLE_REQ (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET + 0x10)
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#define IDLEREQ BIT(31)
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#define DMA_FIRMWARE_CONFIG (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET + 0x14)
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/* Regs for PID Filter */
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#define PIDF_OFFSET 0x2800
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#define PIDF_BASE(n) ((n*4) + PIDF_OFFSET)
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#define PIDF_LEAK_ENABLE (PIDF_OFFSET + 0x100)
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#define PIDF_LEAK_STATUS (PIDF_OFFSET + 0x108)
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#define PIDF_LEAK_COUNT_RESET (PIDF_OFFSET + 0x110)
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#define PIDF_LEAK_COUNTER (PIDF_OFFSET + 0x114)
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#endif /* _C8SECTPFE_CORE_H_ */
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