[MIPS] Kill tlb-andes.c.
Basically identical to c-r4k.c, so maintaining one is really enough.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Thiemo Seufer
Ralf Baechle
Родитель
a3dddd560e
Коммит
c6281edb1d
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@ -12,7 +12,7 @@ obj-$(CONFIG_HIGHMEM) += highmem.o
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obj-$(CONFIG_CPU_MIPS32) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
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obj-$(CONFIG_CPU_MIPS64) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
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obj-$(CONFIG_CPU_NEVADA) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
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obj-$(CONFIG_CPU_R10000) += c-r4k.o cex-gen.o pg-r4k.o tlb-andes.o
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obj-$(CONFIG_CPU_R10000) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
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obj-$(CONFIG_CPU_R3000) += c-r3k.o tlb-r3k.o pg-r4k.o
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obj-$(CONFIG_CPU_R4300) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
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obj-$(CONFIG_CPU_R4X00) += c-r4k.o cex-gen.o pg-r4k.o tlb-r4k.o
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@ -1,259 +0,0 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1997, 1998, 1999 Ralf Baechle (ralf@gnu.org)
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* Copyright (C) 1999 Silicon Graphics, Inc.
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* Copyright (C) 2000 Kanoj Sarcar (kanoj@sgi.com)
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/system.h>
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#include <asm/mmu_context.h>
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extern void build_tlb_refill_handler(void);
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#define NTLB_ENTRIES 64
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#define NTLB_ENTRIES_HALF 32
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void local_flush_tlb_all(void)
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{
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unsigned long flags;
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unsigned long old_ctx;
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unsigned long entry;
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local_irq_save(flags);
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/* Save old context and create impossible VPN2 value */
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old_ctx = read_c0_entryhi() & ASID_MASK;
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write_c0_entryhi(CKSEG0);
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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entry = read_c0_wired();
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/* Blast 'em all away. */
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while (entry < NTLB_ENTRIES) {
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write_c0_index(entry);
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tlb_write_indexed();
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entry++;
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}
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write_c0_entryhi(old_ctx);
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local_irq_restore(flags);
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}
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void local_flush_tlb_mm(struct mm_struct *mm)
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{
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int cpu = smp_processor_id();
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if (cpu_context(cpu, mm) != 0) {
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drop_mmu_context(mm,cpu);
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}
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}
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void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
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unsigned long end)
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{
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struct mm_struct *mm = vma->vm_mm;
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int cpu = smp_processor_id();
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if (cpu_context(cpu, mm) != 0) {
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unsigned long flags;
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int size;
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local_irq_save(flags);
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
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size = (size + 1) >> 1;
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if (size <= NTLB_ENTRIES_HALF) {
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int oldpid = (read_c0_entryhi() & ASID_MASK);
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int newpid = (cpu_context(smp_processor_id(), mm)
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& ASID_MASK);
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start &= (PAGE_MASK << 1);
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end += ((PAGE_SIZE << 1) - 1);
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end &= (PAGE_MASK << 1);
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while(start < end) {
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int idx;
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write_c0_entryhi(start | newpid);
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start += (PAGE_SIZE << 1);
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tlb_probe();
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idx = read_c0_index();
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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write_c0_entryhi(CKSEG0);
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if(idx < 0)
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continue;
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tlb_write_indexed();
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}
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write_c0_entryhi(oldpid);
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} else {
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drop_mmu_context(mm, cpu);
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}
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local_irq_restore(flags);
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}
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}
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void local_flush_tlb_kernel_range(unsigned long start, unsigned long end)
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{
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unsigned long flags;
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int size;
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size = (end - start + (PAGE_SIZE - 1)) >> PAGE_SHIFT;
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size = (size + 1) >> 1;
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local_irq_save(flags);
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if (size <= NTLB_ENTRIES_HALF) {
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int pid = read_c0_entryhi();
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start &= (PAGE_MASK << 1);
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end += ((PAGE_SIZE << 1) - 1);
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end &= (PAGE_MASK << 1);
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while (start < end) {
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int idx;
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write_c0_entryhi(start);
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start += (PAGE_SIZE << 1);
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tlb_probe();
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idx = read_c0_index();
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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write_c0_entryhi(CKSEG0 + (idx << (PAGE_SHIFT+1)));
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if (idx < 0)
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continue;
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tlb_write_indexed();
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}
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write_c0_entryhi(pid);
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} else {
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local_flush_tlb_all();
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}
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local_irq_restore(flags);
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}
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void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
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{
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if (cpu_context(smp_processor_id(), vma->vm_mm) != 0) {
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unsigned long flags;
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int oldpid, newpid, idx;
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newpid = (cpu_context(smp_processor_id(), vma->vm_mm) &
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ASID_MASK);
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page &= (PAGE_MASK << 1);
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local_irq_save(flags);
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oldpid = (read_c0_entryhi() & ASID_MASK);
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write_c0_entryhi(page | newpid);
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tlb_probe();
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idx = read_c0_index();
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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write_c0_entryhi(CKSEG0);
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if (idx < 0)
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goto finish;
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tlb_write_indexed();
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finish:
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write_c0_entryhi(oldpid);
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local_irq_restore(flags);
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}
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}
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/*
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* This one is only used for pages with the global bit set so we don't care
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* much about the ASID.
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*/
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void local_flush_tlb_one(unsigned long page)
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{
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unsigned long flags;
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int oldpid, idx;
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local_irq_save(flags);
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page &= (PAGE_MASK << 1);
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oldpid = read_c0_entryhi() & 0xff;
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write_c0_entryhi(page);
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tlb_probe();
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idx = read_c0_index();
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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if (idx >= 0) {
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/* Make sure all entries differ. */
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write_c0_entryhi(CKSEG0+(idx<<(PAGE_SHIFT+1)));
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tlb_write_indexed();
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}
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write_c0_entryhi(oldpid);
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local_irq_restore(flags);
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}
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/* XXX Simplify this. On the R10000 writing a TLB entry for an virtual
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address that already exists will overwrite the old entry and not result
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in TLB malfunction or TLB shutdown. */
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void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte)
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{
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unsigned long flags;
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pgd_t *pgdp;
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pud_t *pudp;
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pmd_t *pmdp;
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pte_t *ptep;
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int idx, pid;
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/*
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* Handle debugger faulting in for debugee.
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*/
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if (current->active_mm != vma->vm_mm)
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return;
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pid = read_c0_entryhi() & ASID_MASK;
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if ((pid != (cpu_context(smp_processor_id(), vma->vm_mm) & ASID_MASK))
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|| (cpu_context(smp_processor_id(), vma->vm_mm) == 0)) {
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printk(KERN_WARNING
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"%s: Wheee, bogus tlbpid mmpid=%d tlbpid=%d\n",
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__FUNCTION__, (int) (cpu_context(smp_processor_id(),
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vma->vm_mm) & ASID_MASK), pid);
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}
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local_irq_save(flags);
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address &= (PAGE_MASK << 1);
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write_c0_entryhi(address | (pid));
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pgdp = pgd_offset(vma->vm_mm, address);
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tlb_probe();
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pudp = pud_offset(pgdp, address);
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pmdp = pmd_offset(pudp, address);
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idx = read_c0_index();
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ptep = pte_offset_map(pmdp, address);
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write_c0_entrylo0(pte_val(*ptep++) >> 6);
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write_c0_entrylo1(pte_val(*ptep) >> 6);
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write_c0_entryhi(address | pid);
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if (idx < 0) {
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tlb_write_random();
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} else {
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tlb_write_indexed();
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}
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write_c0_entryhi(pid);
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local_irq_restore(flags);
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}
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void __init tlb_init(void)
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{
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/*
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* You should never change this register:
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* - On R4600 1.7 the tlbp never hits for pages smaller than
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* the value in the c0_pagemask register.
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* - The entire mm handling assumes the c0_pagemask register to
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* be set for 4kb pages.
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*/
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write_c0_pagemask(PM_4K);
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write_c0_wired(0);
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write_c0_framemask(0);
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/* From this point on the ARC firmware is dead. */
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local_flush_tlb_all();
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/* Did I tell you that ARC SUCKS? */
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build_tlb_refill_handler();
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}
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@ -424,8 +424,13 @@ void __init tlb_init(void)
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probe_tlb(config);
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write_c0_pagemask(PM_DEFAULT_MASK);
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write_c0_wired(0);
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write_c0_framemask(0);
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temp_tlb_entry = current_cpu_data.tlbsize - 1;
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/* From this point on the ARC firmware is dead. */
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local_flush_tlb_all();
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/* Did I tell you that ARC SUCKS? */
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build_tlb_refill_handler();
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}
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