mtd: nand: omap: combine different flavours of 1-bit hamming ecc schemes
OMAP NAND driver currently supports multiple flavours of 1-bit Hamming ecc-scheme, like: - OMAP_ECC_HAMMING_CODE_DEFAULT 1-bit hamming ecc code using software library - OMAP_ECC_HAMMING_CODE_HW 1-bit hamming ecc-code using GPMC h/w engine - OMAP_ECC_HAMMING_CODE_HW_ROMCODE 1-bit hamming ecc-code using GPMC h/w engin with ecc-layout compatible to ROM code. This patch combines above multiple ecc-schemes into single implementation: - OMAP_ECC_HAM1_CODE_HW 1-bit hamming ecc-code using GPMC h/w engine with ROM-code compatible ecc-layout. Signed-off-by: Pekon Gupta <pekon@ti.com> Reviewed-by: Felipe Balbi <balbi@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
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@ -22,10 +22,10 @@ Optional properties:
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width of 8 is assumed.
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- ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
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"sw" Software method (default)
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"hw" Hardware method
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"hw-romcode" gpmc hamming mode method & romcode layout
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"sw" <deprecated> use "ham1" instead
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"hw" <deprecated> use "ham1" instead
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"hw-romcode" <deprecated> use "ham1" instead
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"ham1" 1-bit Hamming ecc code
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"bch4" 4-bit BCH ecc code
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"bch8" 8-bit BCH ecc code
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@ -142,7 +142,7 @@ __init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
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board_nand_data.nr_parts = nr_parts;
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board_nand_data.devsize = nand_type;
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board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
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board_nand_data.ecc_opt = OMAP_ECC_BCH8_CODE_HW;
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gpmc_nand_init(&board_nand_data, gpmc_t);
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}
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#endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
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@ -1993,10 +1993,7 @@ static int omap_nand_probe(struct platform_device *pdev)
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}
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/* select the ecc type */
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if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_DEFAULT)
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info->nand.ecc.mode = NAND_ECC_SOFT;
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else if ((pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW) ||
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(pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE)) {
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if (pdata->ecc_opt == OMAP_ECC_HAM1_CODE_HW) {
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info->nand.ecc.bytes = 3;
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info->nand.ecc.size = 512;
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info->nand.ecc.strength = 1;
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@ -2025,7 +2022,7 @@ static int omap_nand_probe(struct platform_device *pdev)
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}
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/* rom code layout */
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if (pdata->ecc_opt == OMAP_ECC_HAMMING_CODE_HW_ROMCODE) {
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if (pdata->ecc_opt == OMAP_ECC_HAM1_CODE_HW) {
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if (info->nand.options & NAND_BUSWIDTH_16)
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offset = 2;
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@ -2033,7 +2030,7 @@ static int omap_nand_probe(struct platform_device *pdev)
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offset = 1;
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info->nand.badblock_pattern = &bb_descrip_flashbased;
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}
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omap_oobinfo.eccbytes = 3 * (info->mtd.oobsize/16);
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omap_oobinfo.eccbytes = 3 * (info->mtd.writesize / 512);
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for (i = 0; i < omap_oobinfo.eccbytes; i++)
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omap_oobinfo.eccpos[i] = i+offset;
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@ -23,13 +23,8 @@ enum nand_io {
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};
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enum omap_ecc {
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/* 1-bit ecc: stored at end of spare area */
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OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */
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OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
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/* 1-bit ecc: stored at beginning of spare area as romcode */
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OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */
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/* 1-bit ECC calculation by GPMC, Error detection by Software */
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OMAP_ECC_HAM1_CODE_HW,
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OMAP_ECC_HAM1_CODE_HW = 0,
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/* 4-bit ECC calculation by GPMC, Error detection by Software */
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OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,
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/* 4-bit ECC calculation by GPMC, Error detection by ELM */
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