gpio: bcm-kona: make use of raw_spinlock variants
The bcm-kona gpio driver currently implements an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by: Julia Cartwright <julia@ni.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Julia Cartwright
Linus Walleij
Родитель
45897809d5
Коммит
c69fcea57e
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@ -67,7 +67,7 @@
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struct bcm_kona_gpio {
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void __iomem *reg_base;
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int num_bank;
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spinlock_t lock;
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raw_spinlock_t lock;
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struct gpio_chip gpio_chip;
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struct irq_domain *irq_domain;
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struct bcm_kona_gpio_bank *banks;
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@ -95,13 +95,13 @@ static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,
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unsigned long flags;
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int bank_id = GPIO_BANK(gpio);
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spin_lock_irqsave(&kona_gpio->lock, flags);
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
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val |= BIT(gpio);
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bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
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spin_unlock_irqrestore(&kona_gpio->lock, flags);
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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}
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static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio,
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@ -111,13 +111,13 @@ static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio,
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unsigned long flags;
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int bank_id = GPIO_BANK(gpio);
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spin_lock_irqsave(&kona_gpio->lock, flags);
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
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val &= ~BIT(gpio);
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bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
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spin_unlock_irqrestore(&kona_gpio->lock, flags);
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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}
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static int bcm_kona_gpio_get_dir(struct gpio_chip *chip, unsigned gpio)
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@ -141,7 +141,7 @@ static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
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kona_gpio = gpiochip_get_data(chip);
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reg_base = kona_gpio->reg_base;
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spin_lock_irqsave(&kona_gpio->lock, flags);
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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/* this function only applies to output pin */
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if (bcm_kona_gpio_get_dir(chip, gpio) == GPIOF_DIR_IN)
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@ -154,7 +154,7 @@ static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
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writel(val, reg_base + reg_offset);
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out:
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spin_unlock_irqrestore(&kona_gpio->lock, flags);
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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}
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static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
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@ -168,7 +168,7 @@ static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
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kona_gpio = gpiochip_get_data(chip);
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reg_base = kona_gpio->reg_base;
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spin_lock_irqsave(&kona_gpio->lock, flags);
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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if (bcm_kona_gpio_get_dir(chip, gpio) == GPIOF_DIR_IN)
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reg_offset = GPIO_IN_STATUS(bank_id);
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@ -178,7 +178,7 @@ static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
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/* read the GPIO bank status */
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val = readl(reg_base + reg_offset);
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spin_unlock_irqrestore(&kona_gpio->lock, flags);
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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/* return the specified bit status */
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return !!(val & BIT(bit));
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@ -208,14 +208,14 @@ static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
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kona_gpio = gpiochip_get_data(chip);
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reg_base = kona_gpio->reg_base;
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spin_lock_irqsave(&kona_gpio->lock, flags);
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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val = readl(reg_base + GPIO_CONTROL(gpio));
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val &= ~GPIO_GPCTR0_IOTR_MASK;
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val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
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writel(val, reg_base + GPIO_CONTROL(gpio));
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spin_unlock_irqrestore(&kona_gpio->lock, flags);
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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return 0;
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}
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@ -232,7 +232,7 @@ static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
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kona_gpio = gpiochip_get_data(chip);
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reg_base = kona_gpio->reg_base;
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spin_lock_irqsave(&kona_gpio->lock, flags);
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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val = readl(reg_base + GPIO_CONTROL(gpio));
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val &= ~GPIO_GPCTR0_IOTR_MASK;
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@ -244,7 +244,7 @@ static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
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val |= BIT(bit);
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writel(val, reg_base + reg_offset);
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spin_unlock_irqrestore(&kona_gpio->lock, flags);
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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return 0;
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}
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@ -288,7 +288,7 @@ static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
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}
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/* spin lock for read-modify-write of the GPIO register */
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spin_lock_irqsave(&kona_gpio->lock, flags);
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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val = readl(reg_base + GPIO_CONTROL(gpio));
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val &= ~GPIO_GPCTR0_DBR_MASK;
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@ -303,7 +303,7 @@ static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
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writel(val, reg_base + GPIO_CONTROL(gpio));
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spin_unlock_irqrestore(&kona_gpio->lock, flags);
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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return 0;
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}
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@ -347,13 +347,13 @@ static void bcm_kona_gpio_irq_ack(struct irq_data *d)
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kona_gpio = irq_data_get_irq_chip_data(d);
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reg_base = kona_gpio->reg_base;
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spin_lock_irqsave(&kona_gpio->lock, flags);
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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val = readl(reg_base + GPIO_INT_STATUS(bank_id));
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val |= BIT(bit);
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writel(val, reg_base + GPIO_INT_STATUS(bank_id));
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spin_unlock_irqrestore(&kona_gpio->lock, flags);
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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}
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static void bcm_kona_gpio_irq_mask(struct irq_data *d)
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@ -368,13 +368,13 @@ static void bcm_kona_gpio_irq_mask(struct irq_data *d)
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kona_gpio = irq_data_get_irq_chip_data(d);
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reg_base = kona_gpio->reg_base;
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spin_lock_irqsave(&kona_gpio->lock, flags);
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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val = readl(reg_base + GPIO_INT_MASK(bank_id));
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val |= BIT(bit);
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writel(val, reg_base + GPIO_INT_MASK(bank_id));
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spin_unlock_irqrestore(&kona_gpio->lock, flags);
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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}
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static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
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@ -389,13 +389,13 @@ static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
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kona_gpio = irq_data_get_irq_chip_data(d);
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reg_base = kona_gpio->reg_base;
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spin_lock_irqsave(&kona_gpio->lock, flags);
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
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val |= BIT(bit);
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writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
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spin_unlock_irqrestore(&kona_gpio->lock, flags);
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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}
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static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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@ -431,14 +431,14 @@ static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
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return -EINVAL;
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}
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spin_lock_irqsave(&kona_gpio->lock, flags);
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raw_spin_lock_irqsave(&kona_gpio->lock, flags);
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val = readl(reg_base + GPIO_CONTROL(gpio));
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val &= ~GPIO_GPCTR0_ITR_MASK;
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val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
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writel(val, reg_base + GPIO_CONTROL(gpio));
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spin_unlock_irqrestore(&kona_gpio->lock, flags);
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raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
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return 0;
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}
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@ -655,7 +655,7 @@ static int bcm_kona_gpio_probe(struct platform_device *pdev)
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bank);
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}
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spin_lock_init(&kona_gpio->lock);
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raw_spin_lock_init(&kona_gpio->lock);
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return 0;
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