phy: qcom-qmp-pcie: add support for sm8350 platform
Add support for a single-lane and two-lane PCIe PHYs found on Qualcomm SM8350 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20221118233242.2904088-7-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Dmitry Baryshkov
Vinod Koul
Родитель
c99649c335
Коммит
c70052739d
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@ -1313,6 +1313,40 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
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};
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static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_tx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
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QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
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QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
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QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
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QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
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};
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static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_rc_rx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
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QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
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QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
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QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
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};
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static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_rx_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
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QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34),
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QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
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};
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static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_tx_tbl[] = {
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QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1),
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QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2),
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QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5),
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QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
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QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
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QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
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};
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static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_pcs_tbl[] = {
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QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x0f),
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};
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static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
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QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
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QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
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@ -2021,6 +2055,80 @@ static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
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.phy_status = PHYSTATUS_4_20,
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};
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static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = {
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.lanes = 1,
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.offsets = &qmp_pcie_offsets_v5,
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.tbls = {
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.serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
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.serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
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.tx = sm8350_qmp_gen3x1_pcie_tx_tbl,
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.tx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_tx_tbl),
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.rx = sm8450_qmp_gen3_pcie_rx_tbl,
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.rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
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.pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
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.pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
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.pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
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.pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
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},
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.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
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.serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl,
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.serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl),
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.rx = sm8350_qmp_gen3x1_pcie_rc_rx_tbl,
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.rx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl),
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},
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.clk_list = sc8280xp_pciephy_clk_l,
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.num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
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.reset_list = sdm845_pciephy_reset_l,
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.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
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.vreg_list = qmp_phy_vreg_l,
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.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
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.regs = sm8250_pcie_regs_layout,
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.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
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.phy_status = PHYSTATUS,
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};
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static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = {
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.lanes = 2,
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.offsets = &qmp_pcie_offsets_v5,
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.tbls = {
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.serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
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.serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
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.tx = sm8350_qmp_gen3x2_pcie_tx_tbl,
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.tx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_tx_tbl),
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.rx = sm8450_qmp_gen3_pcie_rx_tbl,
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.rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
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.pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
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.pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
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.pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,
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.pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),
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},
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.tbls_rc = &(const struct qmp_phy_cfg_tbls) {
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.rx = sm8350_qmp_gen3x2_pcie_rc_rx_tbl,
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.rx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_rx_tbl),
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.pcs = sm8350_qmp_gen3x2_pcie_rc_pcs_tbl,
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.pcs_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_pcs_tbl),
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},
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.clk_list = sc8280xp_pciephy_clk_l,
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.num_clks = ARRAY_SIZE(sc8280xp_pciephy_clk_l),
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.reset_list = sdm845_pciephy_reset_l,
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.num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
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.vreg_list = qmp_phy_vreg_l,
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.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
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.regs = sm8250_pcie_regs_layout,
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.pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
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.phy_status = PHYSTATUS,
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};
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static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
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.lanes = 1,
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@ -2613,7 +2721,11 @@ static int qmp_pcie_parse_dt(struct qmp_pcie *qmp)
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qmp->pipe_clks[0].id = "pipe";
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qmp->pipe_clks[1].id = "pipediv2";
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ret = devm_clk_bulk_get(dev, qmp->num_pipe_clks, qmp->pipe_clks);
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ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks);
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if (ret)
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return ret;
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ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1);
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if (ret)
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return ret;
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@ -2733,6 +2845,12 @@ static const struct of_device_id qmp_pcie_of_match_table[] = {
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}, {
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.compatible = "qcom,sm8250-qmp-modem-pcie-phy",
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.data = &sm8250_qmp_gen3x2_pciephy_cfg,
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}, {
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.compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy",
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.data = &sm8350_qmp_gen3x1_pciephy_cfg,
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}, {
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.compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy",
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.data = &sm8350_qmp_gen3x2_pciephy_cfg,
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}, {
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.compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
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.data = &sm8450_qmp_gen3x1_pciephy_cfg,
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