usb: dwc3: gadget: re-factor dwc3_prepare_trbs()
In order to make it easier to add SG support, let's split the big loop out to its own function. Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
Felipe Balbi
Родитель
898c608678
Коммит
c71fc37c19
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@ -539,6 +539,78 @@ static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
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kfree(req);
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}
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/**
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* dwc3_prepare_one_trb - setup one TRB from one request
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* @dep: endpoint for which this request is prepared
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* @req: dwc3_request pointer
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*/
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static int dwc3_prepare_one_trb(struct dwc3_ep *dep,
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struct dwc3_request *req, unsigned last)
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{
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struct dwc3_trb_hw *trb_hw;
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struct dwc3_trb trb;
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unsigned int cur_slot;
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trb_hw = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
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cur_slot = dep->free_slot;
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dep->free_slot++;
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/* Skip the LINK-TRB on ISOC */
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if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
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usb_endpoint_xfer_isoc(dep->desc))
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return 0;
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dwc3_gadget_move_request_queued(req);
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memset(&trb, 0, sizeof(trb));
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req->trb = trb_hw;
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if (usb_endpoint_xfer_isoc(dep->desc)) {
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trb.isp_imi = true;
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trb.csp = true;
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} else {
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trb.lst = last;
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}
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if (usb_endpoint_xfer_bulk(dep->desc) && dep->stream_capable)
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trb.sid_sofn = req->request.stream_id;
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switch (usb_endpoint_type(dep->desc)) {
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case USB_ENDPOINT_XFER_CONTROL:
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trb.trbctl = DWC3_TRBCTL_CONTROL_SETUP;
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break;
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case USB_ENDPOINT_XFER_ISOC:
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trb.trbctl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
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/* IOC every DWC3_TRB_NUM / 4 so we can refill */
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if (!(cur_slot % (DWC3_TRB_NUM / 4)))
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trb.ioc = last;
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break;
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case USB_ENDPOINT_XFER_BULK:
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case USB_ENDPOINT_XFER_INT:
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trb.trbctl = DWC3_TRBCTL_NORMAL;
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break;
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default:
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/*
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* This is only possible with faulty memory because we
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* checked it already :)
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*/
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BUG();
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}
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trb.length = req->request.length;
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trb.bplh = req->request.dma;
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trb.hwo = true;
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dwc3_trb_to_hw(&trb, trb_hw);
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req->trb_dma = dwc3_trb_dma_offset(dep, trb_hw);
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return 0;
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}
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/*
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* dwc3_prepare_trbs - setup TRBs from requests
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* @dep: endpoint for which requests are being prepared
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@ -552,14 +624,14 @@ static struct dwc3_request *dwc3_prepare_trbs(struct dwc3_ep *dep,
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bool starting)
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{
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struct dwc3_request *req, *n, *ret = NULL;
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struct dwc3_trb_hw *trb_hw;
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struct dwc3_trb trb;
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u32 trbs_left;
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unsigned int last_one = 0;
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BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
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/* the first request must not be queued */
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trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
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/*
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* if busy & slot are equal than it is either full or empty. If we are
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* starting to proceed requests then we are empty. Otherwise we ar
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@ -594,25 +666,11 @@ static struct dwc3_request *dwc3_prepare_trbs(struct dwc3_ep *dep,
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return NULL;
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list_for_each_entry_safe(req, n, &dep->request_list, list) {
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unsigned int last_one = 0;
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unsigned int cur_slot;
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trb_hw = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
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cur_slot = dep->free_slot;
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dep->free_slot++;
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/* Skip the LINK-TRB on ISOC */
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if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
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usb_endpoint_xfer_isoc(dep->desc))
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continue;
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dwc3_gadget_move_request_queued(req);
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memset(&trb, 0, sizeof(trb));
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trbs_left--;
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/* Is our TRB pool empty? */
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if (!trbs_left)
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last_one = 1;
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/* Is this the last request? */
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if (list_empty(&dep->request_list))
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last_one = 1;
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@ -625,57 +683,9 @@ static struct dwc3_request *dwc3_prepare_trbs(struct dwc3_ep *dep,
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* While we're debugging the problem, as a workaround to
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* multiple TRBs handling, use only one TRB at a time.
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*/
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last_one = 1;
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req->trb = trb_hw;
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if (!ret)
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ret = req;
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trb.bplh = req->request.dma;
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if (usb_endpoint_xfer_isoc(dep->desc)) {
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trb.isp_imi = true;
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trb.csp = true;
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} else {
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trb.lst = last_one;
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}
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if (usb_endpoint_xfer_bulk(dep->desc) && dep->stream_capable)
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trb.sid_sofn = req->request.stream_id;
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switch (usb_endpoint_type(dep->desc)) {
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case USB_ENDPOINT_XFER_CONTROL:
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trb.trbctl = DWC3_TRBCTL_CONTROL_SETUP;
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break;
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case USB_ENDPOINT_XFER_ISOC:
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trb.trbctl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
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/* IOC every DWC3_TRB_NUM / 4 so we can refill */
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if (!(cur_slot % (DWC3_TRB_NUM / 4)))
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trb.ioc = last_one;
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break;
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case USB_ENDPOINT_XFER_BULK:
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case USB_ENDPOINT_XFER_INT:
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trb.trbctl = DWC3_TRBCTL_NORMAL;
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break;
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default:
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/*
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* This is only possible with faulty memory because we
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* checked it already :)
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*/
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BUG();
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}
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trb.length = req->request.length;
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trb.hwo = true;
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dwc3_trb_to_hw(&trb, trb_hw);
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req->trb_dma = dwc3_trb_dma_offset(dep, trb_hw);
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if (last_one)
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break;
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dwc3_prepare_one_trb(dep, req, true);
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ret = req;
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break;
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}
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return ret;
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