spi: bcm-qspi: choose sysclk setting based on requested speed
Check requested speed for a given transfer before setting 27MHz or 108Mhz sysclk on SoCs that support both. This way for baud rates below 212Khz we can use 27Mhz clock. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Link: https://lore.kernel.org/r/20211124193353.32311-2-kdasu.kdev@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org>
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c74526f947
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@ -287,6 +287,18 @@ static inline int bcm_qspi_spbr_min(struct bcm_qspi *qspi)
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return 8;
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}
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static u32 bcm_qspi_calc_spbr(u32 clk_speed_hz,
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const struct bcm_qspi_parms *xp)
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{
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u32 spbr = 0;
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/* SPBR = System Clock/(2 * SCK Baud Rate) */
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if (xp->speed_hz)
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spbr = clk_speed_hz / (xp->speed_hz * 2);
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return spbr;
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}
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/* Read qspi controller register*/
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static inline u32 bcm_qspi_read(struct bcm_qspi *qspi, enum base_type type,
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unsigned int offset)
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@ -621,9 +633,17 @@ static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
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spcr |= MSPI_SPCR3_HALFDUPLEX | MSPI_SPCR3_HDOUTTYPE;
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if (bcm_qspi_has_sysclk_108(qspi)) {
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/* SYSCLK_108 */
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spcr |= MSPI_SPCR3_SYSCLKSEL_108;
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qspi->base_clk = MSPI_BASE_FREQ * 4;
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/* check requested baud rate before moving to 108Mhz */
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spbr = bcm_qspi_calc_spbr(MSPI_BASE_FREQ * 4, xp);
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if (spbr > QSPI_SPBR_MAX) {
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/* use SYSCLK_27Mhz for slower baud rates */
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spcr &= ~MSPI_SPCR3_SYSCLKSEL_MASK;
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qspi->base_clk = MSPI_BASE_FREQ;
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} else {
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/* SYSCLK_108Mhz */
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spcr |= MSPI_SPCR3_SYSCLKSEL_108;
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qspi->base_clk = MSPI_BASE_FREQ * 4;
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}
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}
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if (xp->bits_per_word > 16) {
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@ -649,9 +669,9 @@ static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
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bcm_qspi_write(qspi, MSPI, MSPI_SPCR3, spcr);
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}
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if (xp->speed_hz)
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spbr = qspi->base_clk / (2 * xp->speed_hz);
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/* SCK Baud Rate = System Clock/(2 * SPBR) */
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qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2);
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spbr = bcm_qspi_calc_spbr(qspi->base_clk, xp);
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spbr = clamp_val(spbr, bcm_qspi_spbr_min(qspi), QSPI_SPBR_MAX);
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bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spbr);
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