ioat: define descriptor control bit-field
This cleans up a mess of and'ing and or'ing bit definitions, and allows simple assignments from the specified dma_ctrl_flags parameter. Signed-off-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Родитель
77867fff03
Коммит
c7984f4e4e
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@ -472,9 +472,9 @@ static dma_cookie_t ioat1_tx_submit(struct dma_async_tx_descriptor *tx)
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return -ENOMEM;
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}
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hw->ctl = IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
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hw->ctl_f.compl_write = 1;
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if (first->txd.callback) {
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hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN;
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hw->ctl_f.int_en = 1;
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if (first != new) {
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/* move callback into to last desc */
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new->txd.callback = first->txd.callback;
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@ -563,9 +563,9 @@ static dma_cookie_t ioat2_tx_submit(struct dma_async_tx_descriptor *tx)
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return -ENOMEM;
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}
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hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
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hw->ctl_f.compl_write = 1;
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if (first->txd.callback) {
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hw->ctl |= IOAT_DMA_DESCRIPTOR_CTL_INT_GN;
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hw->ctl_f.int_en = 1;
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if (first != new) {
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/* move callback into to last desc */
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new->txd.callback = first->txd.callback;
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@ -878,7 +878,8 @@ ioat2_dma_get_next_descriptor(struct ioat_dma_chan *ioat_chan)
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noop_desc = to_ioat_desc(ioat_chan->used_desc.next);
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/* set size to non-zero value (channel returns error when size is 0) */
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noop_desc->hw->size = NULL_DESC_BUFFER_SIZE;
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noop_desc->hw->ctl = IOAT_DMA_DESCRIPTOR_NUL;
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noop_desc->hw->ctl = 0;
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noop_desc->hw->ctl_f.null = 1;
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noop_desc->hw->src_addr = 0;
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noop_desc->hw->dst_addr = 0;
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@ -1230,6 +1231,7 @@ ioat_dma_is_complete(struct dma_chan *chan, dma_cookie_t cookie,
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static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan)
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{
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struct ioat_desc_sw *desc;
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struct ioat_dma_descriptor *hw;
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spin_lock_bh(&ioat_chan->desc_lock);
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@ -1242,17 +1244,19 @@ static void ioat_dma_start_null_desc(struct ioat_dma_chan *ioat_chan)
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return;
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}
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desc->hw->ctl = IOAT_DMA_DESCRIPTOR_NUL
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| IOAT_DMA_DESCRIPTOR_CTL_INT_GN
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| IOAT_DMA_DESCRIPTOR_CTL_CP_STS;
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hw = desc->hw;
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hw->ctl = 0;
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hw->ctl_f.null = 1;
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hw->ctl_f.int_en = 1;
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hw->ctl_f.compl_write = 1;
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/* set size to non-zero value (channel returns error when size is 0) */
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desc->hw->size = NULL_DESC_BUFFER_SIZE;
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desc->hw->src_addr = 0;
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desc->hw->dst_addr = 0;
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hw->size = NULL_DESC_BUFFER_SIZE;
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hw->src_addr = 0;
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hw->dst_addr = 0;
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async_tx_ack(&desc->txd);
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switch (ioat_chan->device->version) {
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case IOAT_VER_1_2:
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desc->hw->next = 0;
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hw->next = 0;
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list_add_tail(&desc->node, &ioat_chan->used_desc);
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writel(((u64) desc->txd.phys) & 0x00000000FFFFFFFF,
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@ -40,7 +40,24 @@
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struct ioat_dma_descriptor {
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uint32_t size;
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uint32_t ctl;
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union {
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uint32_t ctl;
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struct {
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unsigned int int_en:1;
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unsigned int src_snoop_dis:1;
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unsigned int dest_snoop_dis:1;
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unsigned int compl_write:1;
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unsigned int fence:1;
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unsigned int null:1;
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unsigned int src_brk:1;
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unsigned int dest_brk:1;
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unsigned int bundle:1;
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unsigned int dest_dca:1;
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unsigned int hint:1;
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unsigned int rsvd2:13;
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unsigned int op:8;
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} ctl_f;
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};
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uint64_t src_addr;
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uint64_t dst_addr;
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uint64_t next;
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@ -49,23 +66,4 @@ struct ioat_dma_descriptor {
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uint64_t user1;
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uint64_t user2;
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};
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#define IOAT_DMA_DESCRIPTOR_CTL_INT_GN 0x00000001
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#define IOAT_DMA_DESCRIPTOR_CTL_SRC_SN 0x00000002
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#define IOAT_DMA_DESCRIPTOR_CTL_DST_SN 0x00000004
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#define IOAT_DMA_DESCRIPTOR_CTL_CP_STS 0x00000008
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#define IOAT_DMA_DESCRIPTOR_CTL_FRAME 0x00000010
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#define IOAT_DMA_DESCRIPTOR_NUL 0x00000020
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#define IOAT_DMA_DESCRIPTOR_CTL_SP_BRK 0x00000040
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#define IOAT_DMA_DESCRIPTOR_CTL_DP_BRK 0x00000080
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#define IOAT_DMA_DESCRIPTOR_CTL_BNDL 0x00000100
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#define IOAT_DMA_DESCRIPTOR_CTL_DCA 0x00000200
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#define IOAT_DMA_DESCRIPTOR_CTL_BUFHINT 0x00000400
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#define IOAT_DMA_DESCRIPTOR_CTL_OPCODE_CONTEXT 0xFF000000
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#define IOAT_DMA_DESCRIPTOR_CTL_OPCODE_DMA 0x00000000
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#define IOAT_DMA_DESCRIPTOR_CTL_CONTEXT_DCA 0x00000001
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#define IOAT_DMA_DESCRIPTOR_CTL_OPCODE_MASK 0xFF000000
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#endif
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