Merge branch 'am65-cpsw-add-taprio-EST-offload-support'
Murali Karicheri says:
====================
am65-cpsw: add taprio/EST offload support
AM65 CPSW h/w supports Enhanced Scheduled Traffic (EST – defined
in P802.1Qbv/D2.2 that later got included in IEEE 802.1Q-2018)
configuration. EST allows express queue traffic to be scheduled
(placed) on the wire at specific repeatable time intervals. In
Linux kernel, EST configuration is done through tc command and
the taprio scheduler in the net core implements a software only
scheduler (SCH_TAPRIO). If the NIC is capable of EST configuration,
user indicate "flag 2" in the command which is then parsed by
taprio scheduler in net core and indicate that the command is to
be offloaded to h/w. taprio then offloads the command to the
driver by calling ndo_setup_tc() ndo ops. This patch implements
ndo_setup_tc() as well as other changes required to offload EST
configuration to CPSW h/w
For more details please refer patch 2/2.
This series is based on original work done by Ivan Khoronzhuk
<ivan.khoronzhuk@linaro.org> to add taprio offload support to
AM65 CPSW 2G.
1. Example configuration 3 Gates
ifconfig eth0 down
ethtool -L eth0 tx 3
ethtool --set-priv-flags eth0 p0-rx-ptype-rrobin off
ifconfig eth0 192.168.2.20
tc qdisc replace dev eth0 parent root handle 100 taprio \
num_tc 3 \
map 0 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 \
queues 1@0 1@1 1@2 \
base-time 0000 \
sched-entry S 4 125000 \
sched-entry S 2 125000 \
sched-entry S 1 250000 \
flags 2
2. Example configuration 8 Gates
ifconfig eth0 down
ethtool -L eth0 tx 8
ethtool --set-priv-flags eth0 p0-rx-ptype-rrobin off
ifconfig eth0 192.168.2.20
tc qdisc replace dev eth0 parent root handle 100 taprio \
num_tc 8 \
map 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 \
queues 1@0 1@1 1@2 1@3 1@4 1@5 1@6 1@7 \
base-time 0000 \
sched-entry S 80 125000 \
sched-entry S 40 125000 \
sched-entry S 20 125000 \
sched-entry S 10 125000 \
sched-entry S 08 125000 \
sched-entry S 04 125000 \
sched-entry S 02 125000 \
sched-entry S 01 125000 \
flags 2
Classify frames to particular priority using skbedit so that they land at
a specific queue in cpsw h/w which is Gated by the EST gate which opens based
on the sched-entry.
tc qdisc add dev eth0 clsact
In the below for example an iperf3 session with destination port 5007
will go through Q7.
tc filter add dev eth0 egress protocol ip prio 1 u32 match ip dport 5007 0xffff action skbedit priority 7
tc filter add dev eth0 egress protocol ip prio 1 u32 match ip dport 5006 0xffff action skbedit priority 6
tc filter add dev eth0 egress protocol ip prio 1 u32 match ip dport 5005 0xffff action skbedit priority 5
tc filter add dev eth0 egress protocol ip prio 1 u32 match ip dport 5004 0xffff action skbedit priority 4
tc filter add dev eth0 egress protocol ip prio 1 u32 match ip dport 5003 0xffff action skbedit priority 3
tc filter add dev eth0 egress protocol ip prio 1 u32 match ip dport 5002 0xffff action skbedit priority 2
tc filter add dev eth0 egress protocol ip prio 1 u32 match ip dport 5001 0xffff action skbedit priority 1
iperf3 -c 192.168.2.10 -u -l1470 -b32M -t1 -p 5007
Testing was done by capturing frames at the PC using wireshark and checking for
the bust interval or cycle time of UDP frames with a specific port number.
Verified that the distance between first frame of a burst (cycle-time) is 1
milli second and burst duration is within 125 usec based on the received packet
timestamp shown in wireshark packet display.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
Коммит
c7ad365761
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@ -123,6 +123,15 @@ config TI_K3_AM65_CPTS
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protocol, Ethernet Enhanced Scheduled Traffic Operations (CPTS_ESTFn)
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and PCIe Subsystem Precision Time Measurement (PTM).
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config TI_AM65_CPSW_TAS
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bool "Enable TAS offload in AM65 CPSW"
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depends on TI_K3_AM65_CPSW_NUSS && NET_SCH_TAPRIO && TI_K3_AM65_CPTS
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help
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Say y here to support Time Aware Shaper(TAS) offload in AM65 CPSW.
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AM65 CPSW hardware supports Enhanced Scheduled Traffic (EST)
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defined in IEEE 802.1Q 2018. The EST scheduler runs on CPTS and the
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TAS/EST schedule is updated in the Fetch RAM memory of the CPSW.
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config TI_KEYSTONE_NETCP
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tristate "TI Keystone NETCP Core Support"
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select TI_DAVINCI_MDIO
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@ -25,5 +25,5 @@ obj-$(CONFIG_TI_KEYSTONE_NETCP_ETHSS) += keystone_netcp_ethss.o
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keystone_netcp_ethss-y := netcp_ethss.o netcp_sgmii.o netcp_xgbepcsr.o cpsw_ale.o
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obj-$(CONFIG_TI_K3_AM65_CPSW_NUSS) += ti-am65-cpsw-nuss.o
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ti-am65-cpsw-nuss-y := am65-cpsw-nuss.o cpsw_sl.o am65-cpsw-ethtool.o cpsw_ale.o k3-cppi-desc-pool.o
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ti-am65-cpsw-nuss-y := am65-cpsw-nuss.o cpsw_sl.o am65-cpsw-ethtool.o cpsw_ale.o k3-cppi-desc-pool.o am65-cpsw-qos.o
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obj-$(CONFIG_TI_K3_AM65_CPTS) += am65-cpts.o
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@ -730,9 +730,17 @@ static u32 am65_cpsw_get_ethtool_priv_flags(struct net_device *ndev)
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static int am65_cpsw_set_ethtool_priv_flags(struct net_device *ndev, u32 flags)
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{
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struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
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int rrobin;
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common->pf_p0_rx_ptype_rrobin =
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!!(flags & AM65_CPSW_PRIV_P0_RX_PTYPE_RROBIN);
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rrobin = !!(flags & AM65_CPSW_PRIV_P0_RX_PTYPE_RROBIN);
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if (common->est_enabled && rrobin) {
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netdev_err(ndev,
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"p0-rx-ptype-rrobin flag conflicts with QOS\n");
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return -EINVAL;
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}
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common->pf_p0_rx_ptype_rrobin = rrobin;
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am65_cpsw_nuss_set_p0_ptype(common);
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return 0;
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@ -37,12 +37,14 @@
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#define AM65_CPSW_XGMII_BASE 0x2100
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#define AM65_CPSW_CPSW_NU_BASE 0x20000
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#define AM65_CPSW_NU_PORTS_BASE 0x1000
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#define AM65_CPSW_NU_FRAM_BASE 0x12000
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#define AM65_CPSW_NU_STATS_BASE 0x1a000
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#define AM65_CPSW_NU_ALE_BASE 0x1e000
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#define AM65_CPSW_NU_CPTS_BASE 0x1d000
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#define AM65_CPSW_NU_PORTS_OFFSET 0x1000
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#define AM65_CPSW_NU_STATS_PORT_OFFSET 0x200
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#define AM65_CPSW_NU_FRAM_PORT_OFFSET 0x200
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#define AM65_CPSW_MAX_PORTS 8
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@ -188,9 +190,11 @@ void am65_cpsw_nuss_adjust_link(struct net_device *ndev)
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cpsw_ale_control_set(common->ale, port->port_id,
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ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
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am65_cpsw_qos_link_up(ndev, phy->speed);
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netif_tx_wake_all_queues(ndev);
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} else {
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int tmo;
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/* disable forwarding */
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cpsw_ale_control_set(common->ale, port->port_id,
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ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
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@ -204,6 +208,7 @@ void am65_cpsw_nuss_adjust_link(struct net_device *ndev)
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cpsw_sl_ctl_reset(port->slave.mac_sl);
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am65_cpsw_qos_link_down(ndev);
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netif_tx_stop_all_queues(ndev);
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}
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@ -1378,6 +1383,7 @@ static const struct net_device_ops am65_cpsw_nuss_netdev_ops_2g = {
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.ndo_vlan_rx_kill_vid = am65_cpsw_nuss_ndo_slave_kill_vid,
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.ndo_do_ioctl = am65_cpsw_nuss_ndo_slave_ioctl,
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.ndo_set_features = am65_cpsw_nuss_ndo_slave_set_features,
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.ndo_setup_tc = am65_cpsw_qos_ndo_setup_tc,
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};
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static void am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port *port)
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@ -1739,6 +1745,9 @@ static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common)
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port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE +
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(AM65_CPSW_NU_STATS_PORT_OFFSET * port_id);
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port->name = of_get_property(port_np, "label", NULL);
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port->fetch_ram_base =
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common->cpsw_base + AM65_CPSW_NU_FRAM_BASE +
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(AM65_CPSW_NU_FRAM_PORT_OFFSET * (port_id - 1));
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port->disabled = !of_device_is_available(port_np);
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if (port->disabled)
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@ -9,7 +9,9 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/phy.h>
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#include <linux/platform_device.h>
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#include "am65-cpsw-qos.h"
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struct am65_cpts;
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@ -38,10 +40,12 @@ struct am65_cpsw_port {
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u32 port_id;
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void __iomem *port_base;
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void __iomem *stat_base;
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void __iomem *fetch_ram_base;
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bool disabled;
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struct am65_cpsw_slave_data slave;
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bool tx_ts_enabled;
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bool rx_ts_enabled;
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struct am65_cpsw_qos qos;
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};
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struct am65_cpsw_host {
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@ -104,6 +108,7 @@ struct am65_cpsw_common {
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u32 cpsw_ver;
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bool pf_p0_rx_ptype_rrobin;
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struct am65_cpts *cpts;
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int est_enabled;
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};
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struct am65_cpsw_ndev_stats {
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@ -0,0 +1,626 @@
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// SPDX-License-Identifier: GPL-2.0
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/* Texas Instruments K3 AM65 Ethernet QoS submodule
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* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
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*
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* quality of service module includes:
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* Enhanced Scheduler Traffic (EST - P802.1Qbv/D2.2)
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*/
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#include <linux/pm_runtime.h>
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#include <linux/time.h>
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#include "am65-cpsw-nuss.h"
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#include "am65-cpsw-qos.h"
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#include "am65-cpts.h"
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#define AM65_CPSW_REG_CTL 0x004
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#define AM65_CPSW_PN_REG_CTL 0x004
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#define AM65_CPSW_PN_REG_FIFO_STATUS 0x050
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#define AM65_CPSW_PN_REG_EST_CTL 0x060
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/* AM65_CPSW_REG_CTL register fields */
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#define AM65_CPSW_CTL_EST_EN BIT(18)
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/* AM65_CPSW_PN_REG_CTL register fields */
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#define AM65_CPSW_PN_CTL_EST_PORT_EN BIT(17)
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/* AM65_CPSW_PN_REG_EST_CTL register fields */
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#define AM65_CPSW_PN_EST_ONEBUF BIT(0)
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#define AM65_CPSW_PN_EST_BUFSEL BIT(1)
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#define AM65_CPSW_PN_EST_TS_EN BIT(2)
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#define AM65_CPSW_PN_EST_TS_FIRST BIT(3)
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#define AM65_CPSW_PN_EST_ONEPRI BIT(4)
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#define AM65_CPSW_PN_EST_TS_PRI_MSK GENMASK(7, 5)
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/* AM65_CPSW_PN_REG_FIFO_STATUS register fields */
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#define AM65_CPSW_PN_FST_TX_PRI_ACTIVE_MSK GENMASK(7, 0)
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#define AM65_CPSW_PN_FST_TX_E_MAC_ALLOW_MSK GENMASK(15, 8)
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#define AM65_CPSW_PN_FST_EST_CNT_ERR BIT(16)
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#define AM65_CPSW_PN_FST_EST_ADD_ERR BIT(17)
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#define AM65_CPSW_PN_FST_EST_BUFACT BIT(18)
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/* EST FETCH COMMAND RAM */
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#define AM65_CPSW_FETCH_RAM_CMD_NUM 0x80
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#define AM65_CPSW_FETCH_CNT_MSK GENMASK(21, 8)
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#define AM65_CPSW_FETCH_CNT_MAX (AM65_CPSW_FETCH_CNT_MSK >> 8)
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#define AM65_CPSW_FETCH_CNT_OFFSET 8
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#define AM65_CPSW_FETCH_ALLOW_MSK GENMASK(7, 0)
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#define AM65_CPSW_FETCH_ALLOW_MAX AM65_CPSW_FETCH_ALLOW_MSK
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enum timer_act {
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TACT_PROG, /* need program timer */
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TACT_NEED_STOP, /* need stop first */
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TACT_SKIP_PROG, /* just buffer can be updated */
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};
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static int am65_cpsw_port_est_enabled(struct am65_cpsw_port *port)
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{
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return port->qos.est_oper || port->qos.est_admin;
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}
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static void am65_cpsw_est_enable(struct am65_cpsw_common *common, int enable)
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{
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u32 val;
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val = readl(common->cpsw_base + AM65_CPSW_REG_CTL);
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if (enable)
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val |= AM65_CPSW_CTL_EST_EN;
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else
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val &= ~AM65_CPSW_CTL_EST_EN;
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writel(val, common->cpsw_base + AM65_CPSW_REG_CTL);
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common->est_enabled = enable;
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}
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static void am65_cpsw_port_est_enable(struct am65_cpsw_port *port, int enable)
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{
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u32 val;
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val = readl(port->port_base + AM65_CPSW_PN_REG_CTL);
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if (enable)
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val |= AM65_CPSW_PN_CTL_EST_PORT_EN;
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else
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val &= ~AM65_CPSW_PN_CTL_EST_PORT_EN;
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writel(val, port->port_base + AM65_CPSW_PN_REG_CTL);
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}
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/* target new EST RAM buffer, actual toggle happens after cycle completion */
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static void am65_cpsw_port_est_assign_buf_num(struct net_device *ndev,
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int buf_num)
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{
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struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
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u32 val;
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val = readl(port->port_base + AM65_CPSW_PN_REG_EST_CTL);
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if (buf_num)
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val |= AM65_CPSW_PN_EST_BUFSEL;
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else
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val &= ~AM65_CPSW_PN_EST_BUFSEL;
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writel(val, port->port_base + AM65_CPSW_PN_REG_EST_CTL);
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}
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/* am65_cpsw_port_est_is_swapped() - Indicate if h/w is transitioned
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* admin -> oper or not
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*
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* Return true if already transitioned. i.e oper is equal to admin and buf
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* numbers match (est_oper->buf match with est_admin->buf).
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* false if before transition. i.e oper is not equal to admin, (i.e a
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* previous admin command is waiting to be transitioned to oper state
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* and est_oper->buf not match with est_oper->buf).
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*/
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static int am65_cpsw_port_est_is_swapped(struct net_device *ndev, int *oper,
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int *admin)
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{
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struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
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u32 val;
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val = readl(port->port_base + AM65_CPSW_PN_REG_FIFO_STATUS);
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*oper = !!(val & AM65_CPSW_PN_FST_EST_BUFACT);
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val = readl(port->port_base + AM65_CPSW_PN_REG_EST_CTL);
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*admin = !!(val & AM65_CPSW_PN_EST_BUFSEL);
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return *admin == *oper;
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}
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/* am65_cpsw_port_est_get_free_buf_num() - Get free buffer number for
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* Admin to program the new schedule.
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*
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* Logic as follows:-
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* If oper is same as admin, return the other buffer (!oper) as the admin
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* buffer. If oper is not the same, driver let the current oper to continue
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* as it is in the process of transitioning from admin -> oper. So keep the
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* oper by selecting the same oper buffer by writing to EST_BUFSEL bit in
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* EST CTL register. In the second iteration they will match and code returns.
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* The actual buffer to write command is selected later before it is ready
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* to update the schedule.
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*/
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static int am65_cpsw_port_est_get_free_buf_num(struct net_device *ndev)
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{
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int oper, admin;
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int roll = 2;
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while (roll--) {
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if (am65_cpsw_port_est_is_swapped(ndev, &oper, &admin))
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return !oper;
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/* admin is not set, so hinder transition as it's not allowed
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* to touch memory in-flight, by targeting same oper buf.
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*/
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am65_cpsw_port_est_assign_buf_num(ndev, oper);
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dev_info(&ndev->dev,
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"Prev. EST admin cycle is in transit %d -> %d\n",
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oper, admin);
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}
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return admin;
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}
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static void am65_cpsw_admin_to_oper(struct net_device *ndev)
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{
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struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
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if (port->qos.est_oper)
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devm_kfree(&ndev->dev, port->qos.est_oper);
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port->qos.est_oper = port->qos.est_admin;
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port->qos.est_admin = NULL;
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}
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static void am65_cpsw_port_est_get_buf_num(struct net_device *ndev,
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struct am65_cpsw_est *est_new)
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{
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struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
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u32 val;
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val = readl(port->port_base + AM65_CPSW_PN_REG_EST_CTL);
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val &= ~AM65_CPSW_PN_EST_ONEBUF;
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writel(val, port->port_base + AM65_CPSW_PN_REG_EST_CTL);
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est_new->buf = am65_cpsw_port_est_get_free_buf_num(ndev);
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/* rolled buf num means changed buf while configuring */
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if (port->qos.est_oper && port->qos.est_admin &&
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est_new->buf == port->qos.est_oper->buf)
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am65_cpsw_admin_to_oper(ndev);
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}
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static void am65_cpsw_est_set(struct net_device *ndev, int enable)
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{
|
||||
struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
|
||||
struct am65_cpsw_common *common = port->common;
|
||||
int common_enable = 0;
|
||||
int i;
|
||||
|
||||
am65_cpsw_port_est_enable(port, enable);
|
||||
|
||||
for (i = 0; i < common->port_num; i++)
|
||||
common_enable |= am65_cpsw_port_est_enabled(&common->ports[i]);
|
||||
|
||||
common_enable |= enable;
|
||||
am65_cpsw_est_enable(common, common_enable);
|
||||
}
|
||||
|
||||
/* This update is supposed to be used in any routine before getting real state
|
||||
* of admin -> oper transition, particularly it's supposed to be used in some
|
||||
* generic routine for providing real state to Taprio Qdisc.
|
||||
*/
|
||||
static void am65_cpsw_est_update_state(struct net_device *ndev)
|
||||
{
|
||||
struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
|
||||
int oper, admin;
|
||||
|
||||
if (!port->qos.est_admin)
|
||||
return;
|
||||
|
||||
if (!am65_cpsw_port_est_is_swapped(ndev, &oper, &admin))
|
||||
return;
|
||||
|
||||
am65_cpsw_admin_to_oper(ndev);
|
||||
}
|
||||
|
||||
/* Fetch command count it's number of bytes in Gigabit mode or nibbles in
|
||||
* 10/100Mb mode. So, having speed and time in ns, recalculate ns to number of
|
||||
* bytes/nibbles that can be sent while transmission on given speed.
|
||||
*/
|
||||
static int am65_est_cmd_ns_to_cnt(u64 ns, int link_speed)
|
||||
{
|
||||
u64 temp;
|
||||
|
||||
temp = ns * link_speed;
|
||||
if (link_speed < SPEED_1000)
|
||||
temp <<= 1;
|
||||
|
||||
return DIV_ROUND_UP(temp, 8 * 1000);
|
||||
}
|
||||
|
||||
static void __iomem *am65_cpsw_est_set_sched_cmds(void __iomem *addr,
|
||||
int fetch_cnt,
|
||||
int fetch_allow)
|
||||
{
|
||||
u32 prio_mask, cmd_fetch_cnt, cmd;
|
||||
|
||||
do {
|
||||
if (fetch_cnt > AM65_CPSW_FETCH_CNT_MAX) {
|
||||
fetch_cnt -= AM65_CPSW_FETCH_CNT_MAX;
|
||||
cmd_fetch_cnt = AM65_CPSW_FETCH_CNT_MAX;
|
||||
} else {
|
||||
cmd_fetch_cnt = fetch_cnt;
|
||||
/* fetch count can't be less than 16? */
|
||||
if (cmd_fetch_cnt && cmd_fetch_cnt < 16)
|
||||
cmd_fetch_cnt = 16;
|
||||
|
||||
fetch_cnt = 0;
|
||||
}
|
||||
|
||||
prio_mask = fetch_allow & AM65_CPSW_FETCH_ALLOW_MSK;
|
||||
cmd = (cmd_fetch_cnt << AM65_CPSW_FETCH_CNT_OFFSET) | prio_mask;
|
||||
|
||||
writel(cmd, addr);
|
||||
addr += 4;
|
||||
} while (fetch_cnt);
|
||||
|
||||
return addr;
|
||||
}
|
||||
|
||||
static int am65_cpsw_est_calc_cmd_num(struct net_device *ndev,
|
||||
struct tc_taprio_qopt_offload *taprio,
|
||||
int link_speed)
|
||||
{
|
||||
int i, cmd_cnt, cmd_sum = 0;
|
||||
u32 fetch_cnt;
|
||||
|
||||
for (i = 0; i < taprio->num_entries; i++) {
|
||||
if (taprio->entries[i].command != TC_TAPRIO_CMD_SET_GATES) {
|
||||
dev_err(&ndev->dev, "Only SET command is supported");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
fetch_cnt = am65_est_cmd_ns_to_cnt(taprio->entries[i].interval,
|
||||
link_speed);
|
||||
|
||||
cmd_cnt = DIV_ROUND_UP(fetch_cnt, AM65_CPSW_FETCH_CNT_MAX);
|
||||
if (!cmd_cnt)
|
||||
cmd_cnt++;
|
||||
|
||||
cmd_sum += cmd_cnt;
|
||||
|
||||
if (!fetch_cnt)
|
||||
break;
|
||||
}
|
||||
|
||||
return cmd_sum;
|
||||
}
|
||||
|
||||
static int am65_cpsw_est_check_scheds(struct net_device *ndev,
|
||||
struct am65_cpsw_est *est_new)
|
||||
{
|
||||
struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
|
||||
int cmd_num;
|
||||
|
||||
cmd_num = am65_cpsw_est_calc_cmd_num(ndev, &est_new->taprio,
|
||||
port->qos.link_speed);
|
||||
if (cmd_num < 0)
|
||||
return cmd_num;
|
||||
|
||||
if (cmd_num > AM65_CPSW_FETCH_RAM_CMD_NUM / 2) {
|
||||
dev_err(&ndev->dev, "No fetch RAM");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void am65_cpsw_est_set_sched_list(struct net_device *ndev,
|
||||
struct am65_cpsw_est *est_new)
|
||||
{
|
||||
struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
|
||||
u32 fetch_cnt, fetch_allow, all_fetch_allow = 0;
|
||||
void __iomem *ram_addr, *max_ram_addr;
|
||||
struct tc_taprio_sched_entry *entry;
|
||||
int i, ram_size;
|
||||
|
||||
ram_addr = port->fetch_ram_base;
|
||||
ram_size = AM65_CPSW_FETCH_RAM_CMD_NUM * 2;
|
||||
ram_addr += est_new->buf * ram_size;
|
||||
|
||||
max_ram_addr = ram_size + ram_addr;
|
||||
for (i = 0; i < est_new->taprio.num_entries; i++) {
|
||||
entry = &est_new->taprio.entries[i];
|
||||
|
||||
fetch_cnt = am65_est_cmd_ns_to_cnt(entry->interval,
|
||||
port->qos.link_speed);
|
||||
fetch_allow = entry->gate_mask;
|
||||
if (fetch_allow > AM65_CPSW_FETCH_ALLOW_MAX)
|
||||
dev_dbg(&ndev->dev, "fetch_allow > 8 bits: %d\n",
|
||||
fetch_allow);
|
||||
|
||||
ram_addr = am65_cpsw_est_set_sched_cmds(ram_addr, fetch_cnt,
|
||||
fetch_allow);
|
||||
|
||||
if (!fetch_cnt && i < est_new->taprio.num_entries - 1) {
|
||||
dev_info(&ndev->dev,
|
||||
"next scheds after %d have no impact", i + 1);
|
||||
break;
|
||||
}
|
||||
|
||||
all_fetch_allow |= fetch_allow;
|
||||
}
|
||||
|
||||
/* end cmd, enabling non-timed queues for potential over cycle time */
|
||||
if (ram_addr < max_ram_addr)
|
||||
writel(~all_fetch_allow & AM65_CPSW_FETCH_ALLOW_MSK, ram_addr);
|
||||
}
|
||||
|
||||
/**
|
||||
* Enable ESTf periodic output, set cycle start time and interval.
|
||||
*/
|
||||
static int am65_cpsw_timer_set(struct net_device *ndev,
|
||||
struct am65_cpsw_est *est_new)
|
||||
{
|
||||
struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
|
||||
struct am65_cpsw_common *common = port->common;
|
||||
struct am65_cpts *cpts = common->cpts;
|
||||
struct am65_cpts_estf_cfg cfg;
|
||||
|
||||
cfg.ns_period = est_new->taprio.cycle_time;
|
||||
cfg.ns_start = est_new->taprio.base_time;
|
||||
|
||||
return am65_cpts_estf_enable(cpts, port->port_id - 1, &cfg);
|
||||
}
|
||||
|
||||
static void am65_cpsw_timer_stop(struct net_device *ndev)
|
||||
{
|
||||
struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
|
||||
struct am65_cpts *cpts = port->common->cpts;
|
||||
|
||||
am65_cpts_estf_disable(cpts, port->port_id - 1);
|
||||
}
|
||||
|
||||
static enum timer_act am65_cpsw_timer_act(struct net_device *ndev,
|
||||
struct am65_cpsw_est *est_new)
|
||||
{
|
||||
struct tc_taprio_qopt_offload *taprio_oper, *taprio_new;
|
||||
struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
|
||||
struct am65_cpts *cpts = port->common->cpts;
|
||||
u64 cur_time;
|
||||
s64 diff;
|
||||
|
||||
if (!port->qos.est_oper)
|
||||
return TACT_PROG;
|
||||
|
||||
taprio_new = &est_new->taprio;
|
||||
taprio_oper = &port->qos.est_oper->taprio;
|
||||
|
||||
if (taprio_new->cycle_time != taprio_oper->cycle_time)
|
||||
return TACT_NEED_STOP;
|
||||
|
||||
/* in order to avoid timer reset get base_time form oper taprio */
|
||||
if (!taprio_new->base_time && taprio_oper)
|
||||
taprio_new->base_time = taprio_oper->base_time;
|
||||
|
||||
if (taprio_new->base_time == taprio_oper->base_time)
|
||||
return TACT_SKIP_PROG;
|
||||
|
||||
/* base times are cycle synchronized */
|
||||
diff = taprio_new->base_time - taprio_oper->base_time;
|
||||
diff = diff < 0 ? -diff : diff;
|
||||
if (diff % taprio_new->cycle_time)
|
||||
return TACT_NEED_STOP;
|
||||
|
||||
cur_time = am65_cpts_ns_gettime(cpts);
|
||||
if (taprio_new->base_time <= cur_time + taprio_new->cycle_time)
|
||||
return TACT_SKIP_PROG;
|
||||
|
||||
/* TODO: Admin schedule at future time is not currently supported */
|
||||
return TACT_NEED_STOP;
|
||||
}
|
||||
|
||||
static void am65_cpsw_stop_est(struct net_device *ndev)
|
||||
{
|
||||
am65_cpsw_est_set(ndev, 0);
|
||||
am65_cpsw_timer_stop(ndev);
|
||||
}
|
||||
|
||||
static void am65_cpsw_purge_est(struct net_device *ndev)
|
||||
{
|
||||
struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
|
||||
|
||||
am65_cpsw_stop_est(ndev);
|
||||
|
||||
if (port->qos.est_admin)
|
||||
devm_kfree(&ndev->dev, port->qos.est_admin);
|
||||
|
||||
if (port->qos.est_oper)
|
||||
devm_kfree(&ndev->dev, port->qos.est_oper);
|
||||
|
||||
port->qos.est_oper = NULL;
|
||||
port->qos.est_admin = NULL;
|
||||
}
|
||||
|
||||
static int am65_cpsw_configure_taprio(struct net_device *ndev,
|
||||
struct am65_cpsw_est *est_new)
|
||||
{
|
||||
struct am65_cpsw_common *common = am65_ndev_to_common(ndev);
|
||||
struct am65_cpts *cpts = common->cpts;
|
||||
int ret = 0, tact = TACT_PROG;
|
||||
|
||||
am65_cpsw_est_update_state(ndev);
|
||||
|
||||
if (!est_new->taprio.enable) {
|
||||
am65_cpsw_stop_est(ndev);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = am65_cpsw_est_check_scheds(ndev, est_new);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
tact = am65_cpsw_timer_act(ndev, est_new);
|
||||
if (tact == TACT_NEED_STOP) {
|
||||
dev_err(&ndev->dev,
|
||||
"Can't toggle estf timer, stop taprio first");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (tact == TACT_PROG)
|
||||
am65_cpsw_timer_stop(ndev);
|
||||
|
||||
if (!est_new->taprio.base_time)
|
||||
est_new->taprio.base_time = am65_cpts_ns_gettime(cpts);
|
||||
|
||||
am65_cpsw_port_est_get_buf_num(ndev, est_new);
|
||||
am65_cpsw_est_set_sched_list(ndev, est_new);
|
||||
am65_cpsw_port_est_assign_buf_num(ndev, est_new->buf);
|
||||
|
||||
am65_cpsw_est_set(ndev, est_new->taprio.enable);
|
||||
|
||||
if (tact == TACT_PROG) {
|
||||
ret = am65_cpsw_timer_set(ndev, est_new);
|
||||
if (ret) {
|
||||
dev_err(&ndev->dev, "Failed to set cycle time");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void am65_cpsw_cp_taprio(struct tc_taprio_qopt_offload *from,
|
||||
struct tc_taprio_qopt_offload *to)
|
||||
{
|
||||
int i;
|
||||
|
||||
*to = *from;
|
||||
for (i = 0; i < from->num_entries; i++)
|
||||
to->entries[i] = from->entries[i];
|
||||
}
|
||||
|
||||
static int am65_cpsw_set_taprio(struct net_device *ndev, void *type_data)
|
||||
{
|
||||
struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
|
||||
struct tc_taprio_qopt_offload *taprio = type_data;
|
||||
struct am65_cpsw_est *est_new;
|
||||
size_t size;
|
||||
int ret = 0;
|
||||
|
||||
if (taprio->cycle_time_extension) {
|
||||
dev_err(&ndev->dev, "Failed to set cycle time extension");
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
size = sizeof(struct tc_taprio_sched_entry) * taprio->num_entries +
|
||||
sizeof(struct am65_cpsw_est);
|
||||
|
||||
est_new = devm_kzalloc(&ndev->dev, size, GFP_KERNEL);
|
||||
if (!est_new)
|
||||
return -ENOMEM;
|
||||
|
||||
am65_cpsw_cp_taprio(taprio, &est_new->taprio);
|
||||
ret = am65_cpsw_configure_taprio(ndev, est_new);
|
||||
if (!ret) {
|
||||
if (taprio->enable) {
|
||||
if (port->qos.est_admin)
|
||||
devm_kfree(&ndev->dev, port->qos.est_admin);
|
||||
|
||||
port->qos.est_admin = est_new;
|
||||
} else {
|
||||
devm_kfree(&ndev->dev, est_new);
|
||||
am65_cpsw_purge_est(ndev);
|
||||
}
|
||||
} else {
|
||||
devm_kfree(&ndev->dev, est_new);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void am65_cpsw_est_link_up(struct net_device *ndev, int link_speed)
|
||||
{
|
||||
struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
|
||||
ktime_t cur_time;
|
||||
s64 delta;
|
||||
|
||||
port->qos.link_speed = link_speed;
|
||||
if (!am65_cpsw_port_est_enabled(port))
|
||||
return;
|
||||
|
||||
if (port->qos.link_down_time) {
|
||||
cur_time = ktime_get();
|
||||
delta = ktime_us_delta(cur_time, port->qos.link_down_time);
|
||||
if (delta > USEC_PER_SEC) {
|
||||
dev_err(&ndev->dev,
|
||||
"Link has been lost too long, stopping TAS");
|
||||
goto purge_est;
|
||||
}
|
||||
}
|
||||
|
||||
return;
|
||||
|
||||
purge_est:
|
||||
am65_cpsw_purge_est(ndev);
|
||||
}
|
||||
|
||||
static int am65_cpsw_setup_taprio(struct net_device *ndev, void *type_data)
|
||||
{
|
||||
struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
|
||||
struct am65_cpsw_common *common = port->common;
|
||||
|
||||
if (!IS_ENABLED(CONFIG_TI_AM65_CPSW_TAS))
|
||||
return -ENODEV;
|
||||
|
||||
if (!netif_running(ndev)) {
|
||||
dev_err(&ndev->dev, "interface is down, link speed unknown\n");
|
||||
return -ENETDOWN;
|
||||
}
|
||||
|
||||
if (common->pf_p0_rx_ptype_rrobin) {
|
||||
dev_err(&ndev->dev,
|
||||
"p0-rx-ptype-rrobin flag conflicts with taprio qdisc\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (port->qos.link_speed == SPEED_UNKNOWN)
|
||||
return -ENOLINK;
|
||||
|
||||
return am65_cpsw_set_taprio(ndev, type_data);
|
||||
}
|
||||
|
||||
int am65_cpsw_qos_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type,
|
||||
void *type_data)
|
||||
{
|
||||
switch (type) {
|
||||
case TC_SETUP_QDISC_TAPRIO:
|
||||
return am65_cpsw_setup_taprio(ndev, type_data);
|
||||
default:
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
}
|
||||
|
||||
void am65_cpsw_qos_link_up(struct net_device *ndev, int link_speed)
|
||||
{
|
||||
struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
|
||||
|
||||
if (!IS_ENABLED(CONFIG_TI_AM65_CPSW_TAS))
|
||||
return;
|
||||
|
||||
am65_cpsw_est_link_up(ndev, link_speed);
|
||||
port->qos.link_down_time = 0;
|
||||
}
|
||||
|
||||
void am65_cpsw_qos_link_down(struct net_device *ndev)
|
||||
{
|
||||
struct am65_cpsw_port *port = am65_ndev_to_port(ndev);
|
||||
|
||||
if (!IS_ENABLED(CONFIG_TI_AM65_CPSW_TAS))
|
||||
return;
|
||||
|
||||
if (!port->qos.link_down_time)
|
||||
port->qos.link_down_time = ktime_get();
|
||||
|
||||
port->qos.link_speed = SPEED_UNKNOWN;
|
||||
}
|
||||
|
|
@ -0,0 +1,29 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*/
|
||||
|
||||
#ifndef AM65_CPSW_QOS_H_
|
||||
#define AM65_CPSW_QOS_H_
|
||||
|
||||
#include <linux/netdevice.h>
|
||||
#include <net/pkt_sched.h>
|
||||
|
||||
struct am65_cpsw_est {
|
||||
int buf;
|
||||
/* has to be the last one */
|
||||
struct tc_taprio_qopt_offload taprio;
|
||||
};
|
||||
|
||||
struct am65_cpsw_qos {
|
||||
struct am65_cpsw_est *est_admin;
|
||||
struct am65_cpsw_est *est_oper;
|
||||
ktime_t link_down_time;
|
||||
int link_speed;
|
||||
};
|
||||
|
||||
int am65_cpsw_qos_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type,
|
||||
void *type_data);
|
||||
void am65_cpsw_qos_link_up(struct net_device *ndev, int link_speed);
|
||||
void am65_cpsw_qos_link_down(struct net_device *ndev);
|
||||
|
||||
#endif /* AM65_CPSW_QOS_H_ */
|
||||
|
|
@ -450,6 +450,19 @@ static int am65_cpts_ptp_gettimex(struct ptp_clock_info *ptp,
|
|||
return 0;
|
||||
}
|
||||
|
||||
u64 am65_cpts_ns_gettime(struct am65_cpts *cpts)
|
||||
{
|
||||
u64 ns;
|
||||
|
||||
/* reuse ptp_clk_lock as it serialize ts push */
|
||||
mutex_lock(&cpts->ptp_clk_lock);
|
||||
ns = am65_cpts_gettime(cpts, NULL);
|
||||
mutex_unlock(&cpts->ptp_clk_lock);
|
||||
|
||||
return ns;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(am65_cpts_ns_gettime);
|
||||
|
||||
static int am65_cpts_ptp_settime(struct ptp_clock_info *ptp,
|
||||
const struct timespec64 *ts)
|
||||
{
|
||||
|
|
@ -494,6 +507,41 @@ static int am65_cpts_extts_enable(struct am65_cpts *cpts, u32 index, int on)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int am65_cpts_estf_enable(struct am65_cpts *cpts, int idx,
|
||||
struct am65_cpts_estf_cfg *cfg)
|
||||
{
|
||||
u64 cycles;
|
||||
u32 val;
|
||||
|
||||
cycles = cfg->ns_period * cpts->refclk_freq;
|
||||
cycles = DIV_ROUND_UP(cycles, NSEC_PER_SEC);
|
||||
if (cycles > U32_MAX)
|
||||
return -EINVAL;
|
||||
|
||||
/* according to TRM should be zeroed */
|
||||
am65_cpts_write32(cpts, 0, estf[idx].length);
|
||||
|
||||
val = upper_32_bits(cfg->ns_start);
|
||||
am65_cpts_write32(cpts, val, estf[idx].comp_hi);
|
||||
val = lower_32_bits(cfg->ns_start);
|
||||
am65_cpts_write32(cpts, val, estf[idx].comp_lo);
|
||||
val = lower_32_bits(cycles);
|
||||
am65_cpts_write32(cpts, val, estf[idx].length);
|
||||
|
||||
dev_dbg(cpts->dev, "%s: ESTF:%u enabled\n", __func__, idx);
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(am65_cpts_estf_enable);
|
||||
|
||||
void am65_cpts_estf_disable(struct am65_cpts *cpts, int idx)
|
||||
{
|
||||
am65_cpts_write32(cpts, 0, estf[idx].length);
|
||||
|
||||
dev_dbg(cpts->dev, "%s: ESTF:%u disabled\n", __func__, idx);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(am65_cpts_estf_disable);
|
||||
|
||||
static void am65_cpts_perout_enable_hw(struct am65_cpts *cpts,
|
||||
struct ptp_perout_request *req, int on)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -12,6 +12,11 @@
|
|||
|
||||
struct am65_cpts;
|
||||
|
||||
struct am65_cpts_estf_cfg {
|
||||
u64 ns_period;
|
||||
u64 ns_start;
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)
|
||||
struct am65_cpts *am65_cpts_create(struct device *dev, void __iomem *regs,
|
||||
struct device_node *node);
|
||||
|
|
@ -19,6 +24,10 @@ int am65_cpts_phc_index(struct am65_cpts *cpts);
|
|||
void am65_cpts_tx_timestamp(struct am65_cpts *cpts, struct sk_buff *skb);
|
||||
void am65_cpts_prep_tx_timestamp(struct am65_cpts *cpts, struct sk_buff *skb);
|
||||
void am65_cpts_rx_enable(struct am65_cpts *cpts, bool en);
|
||||
u64 am65_cpts_ns_gettime(struct am65_cpts *cpts);
|
||||
int am65_cpts_estf_enable(struct am65_cpts *cpts, int idx,
|
||||
struct am65_cpts_estf_cfg *cfg);
|
||||
void am65_cpts_estf_disable(struct am65_cpts *cpts, int idx);
|
||||
#else
|
||||
static inline struct am65_cpts *am65_cpts_create(struct device *dev,
|
||||
void __iomem *regs,
|
||||
|
|
@ -45,6 +54,21 @@ static inline void am65_cpts_prep_tx_timestamp(struct am65_cpts *cpts,
|
|||
static inline void am65_cpts_rx_enable(struct am65_cpts *cpts, bool en)
|
||||
{
|
||||
}
|
||||
|
||||
static s64 am65_cpts_ns_gettime(struct am65_cpts *cpts)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int am65_cpts_estf_enable(struct am65_cpts *cpts,
|
||||
int idx, struct am65_cpts_estf_cfg *cfg)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void am65_cpts_estf_disable(struct am65_cpts *cpts, int idx)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* K3_CPTS_H_ */
|
||||
|
|
|
|||
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