Samsung Exynos ARM64 improvements for v4.6:
1. Remove separate ARCH_EXYNOS7 symbol and consolidate it into one ARCH_EXYNOS. This depends on clk tree: removal of last presence of ARCH_EXYNOS7. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWz5PsAAoJEME3ZuaGi4PX49cP/jhU8jtgdXvzysVITUPi5Ukv Rl82rmCrrX//z6n2LpHaqG/bg1ynOeaRa8TLYU/4gQ53fORmk4UgtqNvC54/2+KX 2CNdNko85oX7DIc2nr5RwTNEBspYh0lTvChZtzQqoKVRdMJSiv2Ms5FcnMNYDt5q xGlQoriTCzlZjt2q6hjlmSZgy8RIn1EeiwsnP3DzmdiX+POgpItfwKln9Ci7E+oz xGa4N/rdQOA0MeV/wizDyWcaCi8HJSDQfMBq6rvx/NtYSGmJORUggFjmmhfp6wAr tuVMflDX20ZoDrP5XptbHapoTtOpQny/D7TiFhWvNZc59zpLei1GJOUOhWdq1PVH om2D59GZ+cNEzDSM/frJiT7VzB32/d479T8DfrwzUahDC2bj+yDPfSK73T72cERs /eBORjYrjM3h9IEwB4DbE6QrxHondXw3B2PQLq4+40w2sE4efupkiBn6vVKUIT9S Za2n6l1W1D2XQawz37Ya2/rAybkMaTIURgsRXE/Oe7GKz11pS3oRmYSeDWcOnMsw PnVL6uTz5zAtoVRygkRVmPv0JUzZgxlNMKfHy7O1zzhSLBtNwXtzGRNyFO+k1yIk FoWly5/o0mYvW+yU1i5lgBi9Zh5aB5Guq7qsqMoGgDC18u7v+GGAcFhNtwKAXUPy UDf3Ut2RSTitQnyNyl5m =XcED -----END PGP SIGNATURE----- Merge tag 'samsung-soc64-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/arm64 Samsung Exynos ARM64 improvements for v4.6: 1. Remove separate ARCH_EXYNOS7 symbol and consolidate it into one ARCH_EXYNOS. This depends on clk tree: removal of last presence of ARCH_EXYNOS7. * tag 'samsung-soc64-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: arm64: EXYNOS: Consolidate ARCH_EXYNOS7 symbol into ARCH_EXYNOS clk: samsung: Don't build ARMv8 clock drivers on ARMv7 clk: samsung: Enable COMPILE_TEST for Samsung clocks clk: Move vendor's Kconfig into CCF menu section clk: mediatek: Fix memory leak on clock init fail clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h clk: xgene: Remove return from void function clk: xgene: Add SoC and PMD PLL clocks with v2 hardware Documentation: Update APM X-Gene clock binding for v2 hardware clk: s2mps11: remove redundant code clk: s2mps11: remove redundant static variables declaration clk: s2mps11: allocate only one structure for clock init clk: s2mps11: merge two for loops in one clk-divider: make sure read-only dividers do not write to their register clk: tango4: rename ARCH_TANGOX to ARCH_TANGO clk: scpi: Fix checking return value of platform_device_register_simple() clk: mvebu: Mark ioremapped memory as __iomem Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Коммит
c7e1d89b34
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@ -9,6 +9,8 @@ Required properties:
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"apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
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"apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
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"apm,xgene-device-clock" - for a X-Gene device clock
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"apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
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"apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
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Required properties for SoC or PCP PLL clocks:
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- reg : shall be the physical PLL register address for the pll clock.
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@ -15,6 +15,7 @@ config PLAT_S3C24XX
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select NO_IOPORT_MAP
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select S3C_DEV_NAND
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select IRQ_DOMAIN
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select COMMON_CLK
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help
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Base platform code for any Samsung S3C24XX device
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@ -29,21 +29,14 @@ config ARCH_BERLIN
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This enables support for Marvell Berlin SoC Family
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config ARCH_EXYNOS
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bool
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help
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This enables support for Samsung Exynos SoC family
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config ARCH_EXYNOS7
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bool "ARMv8 based Samsung Exynos7"
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select ARCH_EXYNOS
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bool "ARMv8 based Samsung Exynos SoC family"
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select COMMON_CLK_SAMSUNG
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select HAVE_S3C2410_WATCHDOG if WATCHDOG
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select HAVE_S3C_RTC if RTC_CLASS
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select PINCTRL
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select PINCTRL_EXYNOS
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help
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This enables support for Samsung Exynos7 SoC family
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This enables support for ARMv8 based Samsung Exynos SoC family.
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config ARCH_LAYERSCAPE
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bool "ARMv8 based Freescale Layerscape SoC family"
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@ -1,4 +1,4 @@
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dtb-$(CONFIG_ARCH_EXYNOS7) += exynos7-espresso.dtb
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dtb-$(CONFIG_ARCH_EXYNOS) += exynos7-espresso.dtb
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always := $(dtb-y)
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subdir-y := $(dts-dirs)
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@ -34,7 +34,7 @@ CONFIG_ARCH_SUNXI=y
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CONFIG_ARCH_ALPINE=y
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CONFIG_ARCH_BCM_IPROC=y
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CONFIG_ARCH_BERLIN=y
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CONFIG_ARCH_EXYNOS7=y
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CONFIG_ARCH_EXYNOS=y
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CONFIG_ARCH_LAYERSCAPE=y
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CONFIG_ARCH_HISI=y
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CONFIG_ARCH_MEDIATEK=y
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@ -202,11 +202,9 @@ config COMMON_CLK_CDCE706
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source "drivers/clk/bcm/Kconfig"
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source "drivers/clk/hisilicon/Kconfig"
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source "drivers/clk/qcom/Kconfig"
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endmenu
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source "drivers/clk/mvebu/Kconfig"
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source "drivers/clk/qcom/Kconfig"
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source "drivers/clk/samsung/Kconfig"
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source "drivers/clk/tegra/Kconfig"
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endmenu
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@ -43,7 +43,7 @@ obj-$(CONFIG_COMMON_CLK_SI514) += clk-si514.o
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obj-$(CONFIG_COMMON_CLK_SI570) += clk-si570.o
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obj-$(CONFIG_COMMON_CLK_CDCE925) += clk-cdce925.o
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obj-$(CONFIG_ARCH_STM32) += clk-stm32f4.o
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obj-$(CONFIG_ARCH_TANGOX) += clk-tango4.o
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obj-$(CONFIG_ARCH_TANGO) += clk-tango4.o
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obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
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obj-$(CONFIG_ARCH_U300) += clk-u300.o
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obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
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@ -19,8 +19,6 @@
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#include <linux/err.h>
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#include <linux/slab.h>
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#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
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static u8 clk_composite_get_parent(struct clk_hw *hw)
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{
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struct clk_composite *composite = to_clk_composite(hw);
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@ -28,8 +28,6 @@
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* parent - fixed parent. No clk_set_parent support
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*/
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#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
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#define div_mask(width) ((1 << (width)) - 1)
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static unsigned int _get_table_maxdiv(const struct clk_div_table *table,
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@ -423,6 +421,12 @@ const struct clk_ops clk_divider_ops = {
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};
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EXPORT_SYMBOL_GPL(clk_divider_ops);
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const struct clk_ops clk_divider_ro_ops = {
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.recalc_rate = clk_divider_recalc_rate,
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.round_rate = clk_divider_round_rate,
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};
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EXPORT_SYMBOL_GPL(clk_divider_ro_ops);
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static struct clk *_register_divider(struct device *dev, const char *name,
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const char *parent_name, unsigned long flags,
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void __iomem *reg, u8 shift, u8 width,
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@ -446,7 +450,10 @@ static struct clk *_register_divider(struct device *dev, const char *name,
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &clk_divider_ops;
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if (clk_divider_flags & CLK_DIVIDER_READ_ONLY)
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init.ops = &clk_divider_ro_ops;
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else
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init.ops = &clk_divider_ops;
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init.flags = flags | CLK_IS_BASIC;
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init.parent_names = (parent_name ? &parent_name: NULL);
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init.num_parents = (parent_name ? 1 : 0);
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@ -23,8 +23,6 @@
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* parent - fixed parent. No clk_set_parent support
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*/
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#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
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static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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@ -26,8 +26,6 @@
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* parent - fixed parent. No clk_set_parent support
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*/
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#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
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static unsigned long clk_fixed_rate_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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@ -16,8 +16,6 @@
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#include <linux/slab.h>
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#include <linux/rational.h>
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#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
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static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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@ -26,8 +26,6 @@
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* parent - fixed parent. No clk_set_parent support
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*/
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#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
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/*
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* It works on following logic:
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*
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@ -31,8 +31,6 @@
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* parent - fixed parent. No clk_set_parent support
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*/
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#define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw)
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static int clk_gpio_gate_enable(struct clk_hw *hw)
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{
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struct clk_gpio *clk = to_clk_gpio(hw);
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@ -14,8 +14,6 @@
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#include <linux/of.h>
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#include <linux/slab.h>
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#define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
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static unsigned long __get_mult(struct clk_multiplier *mult,
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unsigned long rate,
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unsigned long parent_rate)
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@ -26,8 +26,6 @@
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* parent - parent is adjustable through clk_set_parent
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*/
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#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
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static u8 clk_mux_get_parent(struct clk_hw *hw)
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{
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struct clk_mux *mux = to_clk_mux(hw);
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@ -28,11 +28,6 @@
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#include <linux/mfd/samsung/s5m8767.h>
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#include <linux/mfd/samsung/core.h>
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#define s2mps11_name(a) (a->hw.init->name)
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static struct clk **clk_table;
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static struct clk_onecell_data clk_data;
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enum {
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S2MPS11_CLK_AP = 0,
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S2MPS11_CLK_CP,
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@ -99,6 +94,7 @@ static struct clk_ops s2mps11_clk_ops = {
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.recalc_rate = s2mps11_clk_recalc_rate,
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};
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/* This s2mps11_clks_init tructure is common to s2mps11, s2mps13 and s2mps14 */
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static struct clk_init_data s2mps11_clks_init[S2MPS11_CLKS_NUM] = {
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[S2MPS11_CLK_AP] = {
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.name = "s2mps11_ap",
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@ -117,37 +113,6 @@ static struct clk_init_data s2mps11_clks_init[S2MPS11_CLKS_NUM] = {
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},
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};
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static struct clk_init_data s2mps13_clks_init[S2MPS11_CLKS_NUM] = {
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[S2MPS11_CLK_AP] = {
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.name = "s2mps13_ap",
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.ops = &s2mps11_clk_ops,
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.flags = CLK_IS_ROOT,
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},
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[S2MPS11_CLK_CP] = {
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.name = "s2mps13_cp",
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.ops = &s2mps11_clk_ops,
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.flags = CLK_IS_ROOT,
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},
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[S2MPS11_CLK_BT] = {
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.name = "s2mps13_bt",
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.ops = &s2mps11_clk_ops,
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.flags = CLK_IS_ROOT,
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},
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};
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static struct clk_init_data s2mps14_clks_init[S2MPS11_CLKS_NUM] = {
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[S2MPS11_CLK_AP] = {
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.name = "s2mps14_ap",
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.ops = &s2mps11_clk_ops,
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.flags = CLK_IS_ROOT,
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},
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[S2MPS11_CLK_BT] = {
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.name = "s2mps14_bt",
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.ops = &s2mps11_clk_ops,
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.flags = CLK_IS_ROOT,
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},
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};
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static struct device_node *s2mps11_clk_parse_dt(struct platform_device *pdev,
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struct clk_init_data *clks_init)
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{
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@ -164,12 +129,9 @@ static struct device_node *s2mps11_clk_parse_dt(struct platform_device *pdev,
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return ERR_PTR(-EINVAL);
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}
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for (i = 0; i < S2MPS11_CLKS_NUM; i++) {
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if (!clks_init[i].name)
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continue; /* Skip clocks not present in some devices */
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for (i = 0; i < S2MPS11_CLKS_NUM; i++)
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of_property_read_string_index(clk_np, "clock-output-names", i,
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&clks_init[i].name);
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}
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return clk_np;
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}
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|
@ -177,39 +139,38 @@ static struct device_node *s2mps11_clk_parse_dt(struct platform_device *pdev,
|
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static int s2mps11_clk_probe(struct platform_device *pdev)
|
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{
|
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struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
|
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struct s2mps11_clk *s2mps11_clks, *s2mps11_clk;
|
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struct s2mps11_clk *s2mps11_clks;
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struct clk_onecell_data *clk_data;
|
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unsigned int s2mps11_reg;
|
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struct clk_init_data *clks_init;
|
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int i, ret = 0;
|
||||
enum sec_device_type hwid = platform_get_device_id(pdev)->driver_data;
|
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|
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s2mps11_clks = devm_kcalloc(&pdev->dev, S2MPS11_CLKS_NUM,
|
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sizeof(*s2mps11_clk), GFP_KERNEL);
|
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sizeof(*s2mps11_clks), GFP_KERNEL);
|
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if (!s2mps11_clks)
|
||||
return -ENOMEM;
|
||||
|
||||
s2mps11_clk = s2mps11_clks;
|
||||
|
||||
clk_table = devm_kcalloc(&pdev->dev, S2MPS11_CLKS_NUM,
|
||||
sizeof(struct clk *), GFP_KERNEL);
|
||||
if (!clk_table)
|
||||
clk_data = devm_kzalloc(&pdev->dev, sizeof(*clk_data), GFP_KERNEL);
|
||||
if (!clk_data)
|
||||
return -ENOMEM;
|
||||
|
||||
switch(platform_get_device_id(pdev)->driver_data) {
|
||||
clk_data->clks = devm_kcalloc(&pdev->dev, S2MPS11_CLKS_NUM,
|
||||
sizeof(struct clk *), GFP_KERNEL);
|
||||
if (!clk_data->clks)
|
||||
return -ENOMEM;
|
||||
|
||||
switch (hwid) {
|
||||
case S2MPS11X:
|
||||
s2mps11_reg = S2MPS11_REG_RTC_CTRL;
|
||||
clks_init = s2mps11_clks_init;
|
||||
break;
|
||||
case S2MPS13X:
|
||||
s2mps11_reg = S2MPS13_REG_RTCCTRL;
|
||||
clks_init = s2mps13_clks_init;
|
||||
break;
|
||||
case S2MPS14X:
|
||||
s2mps11_reg = S2MPS14_REG_RTCCTRL;
|
||||
clks_init = s2mps14_clks_init;
|
||||
break;
|
||||
case S5M8767X:
|
||||
s2mps11_reg = S5M8767_REG_CTRL1;
|
||||
clks_init = s2mps11_clks_init;
|
||||
break;
|
||||
default:
|
||||
dev_err(&pdev->dev, "Invalid device type\n");
|
||||
|
@ -217,46 +178,39 @@ static int s2mps11_clk_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
/* Store clocks of_node in first element of s2mps11_clks array */
|
||||
s2mps11_clks->clk_np = s2mps11_clk_parse_dt(pdev, clks_init);
|
||||
s2mps11_clks->clk_np = s2mps11_clk_parse_dt(pdev, s2mps11_clks_init);
|
||||
if (IS_ERR(s2mps11_clks->clk_np))
|
||||
return PTR_ERR(s2mps11_clks->clk_np);
|
||||
|
||||
for (i = 0; i < S2MPS11_CLKS_NUM; i++, s2mps11_clk++) {
|
||||
if (!clks_init[i].name)
|
||||
for (i = 0; i < S2MPS11_CLKS_NUM; i++) {
|
||||
if (i == S2MPS11_CLK_CP && hwid == S2MPS14X)
|
||||
continue; /* Skip clocks not present in some devices */
|
||||
s2mps11_clk->iodev = iodev;
|
||||
s2mps11_clk->hw.init = &clks_init[i];
|
||||
s2mps11_clk->mask = 1 << i;
|
||||
s2mps11_clk->reg = s2mps11_reg;
|
||||
s2mps11_clks[i].iodev = iodev;
|
||||
s2mps11_clks[i].hw.init = &s2mps11_clks_init[i];
|
||||
s2mps11_clks[i].mask = 1 << i;
|
||||
s2mps11_clks[i].reg = s2mps11_reg;
|
||||
|
||||
s2mps11_clk->clk = devm_clk_register(&pdev->dev,
|
||||
&s2mps11_clk->hw);
|
||||
if (IS_ERR(s2mps11_clk->clk)) {
|
||||
s2mps11_clks[i].clk = devm_clk_register(&pdev->dev,
|
||||
&s2mps11_clks[i].hw);
|
||||
if (IS_ERR(s2mps11_clks[i].clk)) {
|
||||
dev_err(&pdev->dev, "Fail to register : %s\n",
|
||||
s2mps11_name(s2mps11_clk));
|
||||
ret = PTR_ERR(s2mps11_clk->clk);
|
||||
s2mps11_clks_init[i].name);
|
||||
ret = PTR_ERR(s2mps11_clks[i].clk);
|
||||
goto err_reg;
|
||||
}
|
||||
|
||||
s2mps11_clk->lookup = clkdev_create(s2mps11_clk->clk,
|
||||
s2mps11_name(s2mps11_clk), NULL);
|
||||
if (!s2mps11_clk->lookup) {
|
||||
s2mps11_clks[i].lookup = clkdev_create(s2mps11_clks[i].clk,
|
||||
s2mps11_clks_init[i].name, NULL);
|
||||
if (!s2mps11_clks[i].lookup) {
|
||||
ret = -ENOMEM;
|
||||
goto err_reg;
|
||||
}
|
||||
clk_data->clks[i] = s2mps11_clks[i].clk;
|
||||
}
|
||||
|
||||
for (i = 0; i < S2MPS11_CLKS_NUM; i++) {
|
||||
/* Skip clocks not present on S2MPS14 */
|
||||
if (!clks_init[i].name)
|
||||
continue;
|
||||
clk_table[i] = s2mps11_clks[i].clk;
|
||||
}
|
||||
|
||||
clk_data.clks = clk_table;
|
||||
clk_data.clk_num = S2MPS11_CLKS_NUM;
|
||||
clk_data->clk_num = S2MPS11_CLKS_NUM;
|
||||
of_clk_add_provider(s2mps11_clks->clk_np, of_clk_src_onecell_get,
|
||||
&clk_data);
|
||||
clk_data);
|
||||
|
||||
platform_set_drvdata(pdev, s2mps11_clks);
|
||||
|
||||
|
|
|
@ -299,7 +299,7 @@ static int scpi_clocks_probe(struct platform_device *pdev)
|
|||
/* Add the virtual cpufreq device */
|
||||
cpufreq_dev = platform_device_register_simple("scpi-cpufreq",
|
||||
-1, NULL, 0);
|
||||
if (!cpufreq_dev)
|
||||
if (IS_ERR(cpufreq_dev))
|
||||
pr_warn("unable to register cpufreq device");
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -29,7 +29,9 @@
|
|||
#include <linux/of_address.h>
|
||||
|
||||
/* Register SCU_PCPPLL bit fields */
|
||||
#define N_DIV_RD(src) (((src) & 0x000001ff))
|
||||
#define N_DIV_RD(src) ((src) & 0x000001ff)
|
||||
#define SC_N_DIV_RD(src) ((src) & 0x0000007f)
|
||||
#define SC_OUTDIV2(src) (((src) & 0x00000100) >> 8)
|
||||
|
||||
/* Register SCU_SOCPLL bit fields */
|
||||
#define CLKR_RD(src) (((src) & 0x07000000)>>24)
|
||||
|
@ -48,7 +50,7 @@ static inline u32 xgene_clk_read(void __iomem *csr)
|
|||
|
||||
static inline void xgene_clk_write(u32 data, void __iomem *csr)
|
||||
{
|
||||
return writel_relaxed(data, csr);
|
||||
writel_relaxed(data, csr);
|
||||
}
|
||||
|
||||
/* PLL Clock */
|
||||
|
@ -63,6 +65,7 @@ struct xgene_clk_pll {
|
|||
spinlock_t *lock;
|
||||
u32 pll_offset;
|
||||
enum xgene_pll_type type;
|
||||
int version;
|
||||
};
|
||||
|
||||
#define to_xgene_clk_pll(_hw) container_of(_hw, struct xgene_clk_pll, hw)
|
||||
|
@ -92,27 +95,37 @@ static unsigned long xgene_clk_pll_recalc_rate(struct clk_hw *hw,
|
|||
|
||||
pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset);
|
||||
|
||||
if (pllclk->type == PLL_TYPE_PCP) {
|
||||
/*
|
||||
* PLL VCO = Reference clock * NF
|
||||
* PCP PLL = PLL_VCO / 2
|
||||
*/
|
||||
nout = 2;
|
||||
fvco = parent_rate * (N_DIV_RD(pll) + 4);
|
||||
if (pllclk->version <= 1) {
|
||||
if (pllclk->type == PLL_TYPE_PCP) {
|
||||
/*
|
||||
* PLL VCO = Reference clock * NF
|
||||
* PCP PLL = PLL_VCO / 2
|
||||
*/
|
||||
nout = 2;
|
||||
fvco = parent_rate * (N_DIV_RD(pll) + 4);
|
||||
} else {
|
||||
/*
|
||||
* Fref = Reference Clock / NREF;
|
||||
* Fvco = Fref * NFB;
|
||||
* Fout = Fvco / NOUT;
|
||||
*/
|
||||
nref = CLKR_RD(pll) + 1;
|
||||
nout = CLKOD_RD(pll) + 1;
|
||||
nfb = CLKF_RD(pll);
|
||||
fref = parent_rate / nref;
|
||||
fvco = fref * nfb;
|
||||
}
|
||||
} else {
|
||||
/*
|
||||
* Fref = Reference Clock / NREF;
|
||||
* Fvco = Fref * NFB;
|
||||
* Fout = Fvco / NOUT;
|
||||
* fvco = Reference clock * FBDIVC
|
||||
* PLL freq = fvco / NOUT
|
||||
*/
|
||||
nref = CLKR_RD(pll) + 1;
|
||||
nout = CLKOD_RD(pll) + 1;
|
||||
nfb = CLKF_RD(pll);
|
||||
fref = parent_rate / nref;
|
||||
fvco = fref * nfb;
|
||||
nout = SC_OUTDIV2(pll) ? 2 : 3;
|
||||
fvco = parent_rate * SC_N_DIV_RD(pll);
|
||||
}
|
||||
pr_debug("%s pll recalc rate %ld parent %ld\n", clk_hw_get_name(hw),
|
||||
fvco / nout, parent_rate);
|
||||
pr_debug("%s pll recalc rate %ld parent %ld version %d\n",
|
||||
clk_hw_get_name(hw), fvco / nout, parent_rate,
|
||||
pllclk->version);
|
||||
|
||||
return fvco / nout;
|
||||
}
|
||||
|
@ -125,7 +138,7 @@ static const struct clk_ops xgene_clk_pll_ops = {
|
|||
static struct clk *xgene_register_clk_pll(struct device *dev,
|
||||
const char *name, const char *parent_name,
|
||||
unsigned long flags, void __iomem *reg, u32 pll_offset,
|
||||
u32 type, spinlock_t *lock)
|
||||
u32 type, spinlock_t *lock, int version)
|
||||
{
|
||||
struct xgene_clk_pll *apmclk;
|
||||
struct clk *clk;
|
||||
|
@ -144,6 +157,7 @@ static struct clk *xgene_register_clk_pll(struct device *dev,
|
|||
init.parent_names = parent_name ? &parent_name : NULL;
|
||||
init.num_parents = parent_name ? 1 : 0;
|
||||
|
||||
apmclk->version = version;
|
||||
apmclk->reg = reg;
|
||||
apmclk->lock = lock;
|
||||
apmclk->pll_offset = pll_offset;
|
||||
|
@ -160,26 +174,37 @@ static struct clk *xgene_register_clk_pll(struct device *dev,
|
|||
return clk;
|
||||
}
|
||||
|
||||
static int xgene_pllclk_version(struct device_node *np)
|
||||
{
|
||||
if (of_device_is_compatible(np, "apm,xgene-socpll-clock"))
|
||||
return 1;
|
||||
if (of_device_is_compatible(np, "apm,xgene-pcppll-clock"))
|
||||
return 1;
|
||||
return 2;
|
||||
}
|
||||
|
||||
static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_type)
|
||||
{
|
||||
const char *clk_name = np->full_name;
|
||||
struct clk *clk;
|
||||
void __iomem *reg;
|
||||
const char *clk_name = np->full_name;
|
||||
struct clk *clk;
|
||||
void __iomem *reg;
|
||||
int version = xgene_pllclk_version(np);
|
||||
|
||||
reg = of_iomap(np, 0);
|
||||
if (reg == NULL) {
|
||||
pr_err("Unable to map CSR register for %s\n", np->full_name);
|
||||
return;
|
||||
}
|
||||
of_property_read_string(np, "clock-output-names", &clk_name);
|
||||
clk = xgene_register_clk_pll(NULL,
|
||||
clk_name, of_clk_get_parent_name(np, 0),
|
||||
CLK_IS_ROOT, reg, 0, pll_type, &clk_lock);
|
||||
if (!IS_ERR(clk)) {
|
||||
of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
||||
clk_register_clkdev(clk, clk_name, NULL);
|
||||
pr_debug("Add %s clock PLL\n", clk_name);
|
||||
}
|
||||
reg = of_iomap(np, 0);
|
||||
if (reg == NULL) {
|
||||
pr_err("Unable to map CSR register for %s\n", np->full_name);
|
||||
return;
|
||||
}
|
||||
of_property_read_string(np, "clock-output-names", &clk_name);
|
||||
clk = xgene_register_clk_pll(NULL,
|
||||
clk_name, of_clk_get_parent_name(np, 0),
|
||||
CLK_IS_ROOT, reg, 0, pll_type, &clk_lock,
|
||||
version);
|
||||
if (!IS_ERR(clk)) {
|
||||
of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
||||
clk_register_clkdev(clk, clk_name, NULL);
|
||||
pr_debug("Add %s clock PLL\n", clk_name);
|
||||
}
|
||||
}
|
||||
|
||||
static void xgene_socpllclk_init(struct device_node *np)
|
||||
|
@ -460,7 +485,7 @@ static void __init xgene_devclk_init(struct device_node *np)
|
|||
rc = of_address_to_resource(np, i, &res);
|
||||
if (rc != 0) {
|
||||
if (i == 0) {
|
||||
pr_err("no DTS register for %s\n",
|
||||
pr_err("no DTS register for %s\n",
|
||||
np->full_name);
|
||||
return;
|
||||
}
|
||||
|
@ -518,4 +543,8 @@ err:
|
|||
|
||||
CLK_OF_DECLARE(xgene_socpll_clock, "apm,xgene-socpll-clock", xgene_socpllclk_init);
|
||||
CLK_OF_DECLARE(xgene_pcppll_clock, "apm,xgene-pcppll-clock", xgene_pcppllclk_init);
|
||||
CLK_OF_DECLARE(xgene_socpll_v2_clock, "apm,xgene-socpll-v2-clock",
|
||||
xgene_socpllclk_init);
|
||||
CLK_OF_DECLARE(xgene_pcppll_v2_clock, "apm,xgene-pcppll-v2-clock",
|
||||
xgene_pcppllclk_init);
|
||||
CLK_OF_DECLARE(xgene_dev_clock, "apm,xgene-device-clock", xgene_devclk_init);
|
||||
|
|
|
@ -38,7 +38,7 @@ struct clk_busy_divider {
|
|||
|
||||
static inline struct clk_busy_divider *to_clk_busy_divider(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_divider *div = container_of(hw, struct clk_divider, hw);
|
||||
struct clk_divider *div = to_clk_divider(hw);
|
||||
|
||||
return container_of(div, struct clk_busy_divider, div);
|
||||
}
|
||||
|
@ -123,7 +123,7 @@ struct clk_busy_mux {
|
|||
|
||||
static inline struct clk_busy_mux *to_clk_busy_mux(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_mux *mux = container_of(hw, struct clk_mux, hw);
|
||||
struct clk_mux *mux = to_clk_mux(hw);
|
||||
|
||||
return container_of(mux, struct clk_busy_mux, mux);
|
||||
}
|
||||
|
|
|
@ -15,7 +15,6 @@
|
|||
#include <linux/slab.h>
|
||||
#include "clk.h"
|
||||
|
||||
#define to_clk_div(_hw) container_of(_hw, struct clk_divider, hw)
|
||||
#define div_mask(d) ((1 << (d->width)) - 1)
|
||||
|
||||
/**
|
||||
|
@ -35,7 +34,7 @@ struct clk_fixup_div {
|
|||
|
||||
static inline struct clk_fixup_div *to_clk_fixup_div(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_divider *divider = to_clk_div(hw);
|
||||
struct clk_divider *divider = to_clk_divider(hw);
|
||||
|
||||
return container_of(divider, struct clk_fixup_div, divider);
|
||||
}
|
||||
|
@ -60,7 +59,7 @@ static int clk_fixup_div_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw);
|
||||
struct clk_divider *div = to_clk_div(hw);
|
||||
struct clk_divider *div = to_clk_divider(hw);
|
||||
unsigned int divider, value;
|
||||
unsigned long flags = 0;
|
||||
u32 val;
|
||||
|
|
|
@ -15,8 +15,6 @@
|
|||
#include <linux/slab.h>
|
||||
#include "clk.h"
|
||||
|
||||
#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
|
||||
|
||||
/**
|
||||
* struct clk_fixup_mux - imx integer fixup multiplexer clock
|
||||
* @mux: the parent class
|
||||
|
|
|
@ -31,7 +31,7 @@ struct clk_gate_exclusive {
|
|||
|
||||
static int clk_gate_exclusive_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_gate *gate = container_of(hw, struct clk_gate, hw);
|
||||
struct clk_gate *gate = to_clk_gate(hw);
|
||||
struct clk_gate_exclusive *exgate = container_of(gate,
|
||||
struct clk_gate_exclusive, gate);
|
||||
u32 val = readl(gate->reg);
|
||||
|
|
|
@ -25,7 +25,7 @@
|
|||
|
||||
static int mtk_cg_bit_is_cleared(struct clk_hw *hw)
|
||||
{
|
||||
struct mtk_clk_gate *cg = to_clk_gate(hw);
|
||||
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
|
||||
u32 val;
|
||||
|
||||
regmap_read(cg->regmap, cg->sta_ofs, &val);
|
||||
|
@ -37,7 +37,7 @@ static int mtk_cg_bit_is_cleared(struct clk_hw *hw)
|
|||
|
||||
static int mtk_cg_bit_is_set(struct clk_hw *hw)
|
||||
{
|
||||
struct mtk_clk_gate *cg = to_clk_gate(hw);
|
||||
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
|
||||
u32 val;
|
||||
|
||||
regmap_read(cg->regmap, cg->sta_ofs, &val);
|
||||
|
@ -49,14 +49,14 @@ static int mtk_cg_bit_is_set(struct clk_hw *hw)
|
|||
|
||||
static void mtk_cg_set_bit(struct clk_hw *hw)
|
||||
{
|
||||
struct mtk_clk_gate *cg = to_clk_gate(hw);
|
||||
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
|
||||
|
||||
regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit));
|
||||
}
|
||||
|
||||
static void mtk_cg_clr_bit(struct clk_hw *hw)
|
||||
{
|
||||
struct mtk_clk_gate *cg = to_clk_gate(hw);
|
||||
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
|
||||
|
||||
regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
|
||||
}
|
||||
|
|
|
@ -29,7 +29,7 @@ struct mtk_clk_gate {
|
|||
u8 bit;
|
||||
};
|
||||
|
||||
static inline struct mtk_clk_gate *to_clk_gate(struct clk_hw *hw)
|
||||
static inline struct mtk_clk_gate *to_mtk_clk_gate(struct clk_hw *hw)
|
||||
{
|
||||
return container_of(hw, struct mtk_clk_gate, hw);
|
||||
}
|
||||
|
|
|
@ -209,12 +209,14 @@ struct clk * __init mtk_clk_register_composite(const struct mtk_composite *mc,
|
|||
mc->flags);
|
||||
|
||||
if (IS_ERR(clk)) {
|
||||
kfree(gate);
|
||||
kfree(mux);
|
||||
ret = PTR_ERR(clk);
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
return clk;
|
||||
err_out:
|
||||
kfree(div);
|
||||
kfree(gate);
|
||||
kfree(mux);
|
||||
|
||||
return ERR_PTR(ret);
|
||||
|
|
|
@ -199,8 +199,6 @@ struct clk_gating_ctrl {
|
|||
u32 saved_reg;
|
||||
};
|
||||
|
||||
#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
|
||||
|
||||
static struct clk_gating_ctrl *ctrl;
|
||||
|
||||
static struct clk *clk_gating_get_src(
|
||||
|
|
|
@ -247,7 +247,7 @@ static struct clk_onecell_data dove_divider_data = {
|
|||
|
||||
void __init dove_divider_clk_init(struct device_node *np)
|
||||
{
|
||||
void *base;
|
||||
void __iomem *base;
|
||||
|
||||
base = of_iomap(np, 0);
|
||||
if (WARN_ON(!base))
|
||||
|
|
|
@ -256,8 +256,6 @@ static const struct clk_muxing_soc_desc kirkwood_mux_desc[] __initconst = {
|
|||
11, 1, 0 },
|
||||
};
|
||||
|
||||
#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
|
||||
|
||||
static struct clk *clk_muxing_get_src(
|
||||
struct of_phandle_args *clkspec, void *data)
|
||||
{
|
||||
|
|
|
@ -33,7 +33,7 @@ struct clk_div {
|
|||
|
||||
static inline struct clk_div *to_clk_div(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_divider *divider = container_of(hw, struct clk_divider, hw);
|
||||
struct clk_divider *divider = to_clk_divider(hw);
|
||||
|
||||
return container_of(divider, struct clk_div, divider);
|
||||
}
|
||||
|
|
|
@ -28,8 +28,6 @@
|
|||
#define CCU_BRANCH_IS_BUS BIT(0)
|
||||
#define CCU_BRANCH_HAVE_DIV2 BIT(1)
|
||||
|
||||
#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
|
||||
|
||||
struct lpc18xx_branch_clk_data {
|
||||
const char **name;
|
||||
int num;
|
||||
|
@ -222,7 +220,7 @@ static void lpc18xx_ccu_register_branch_gate_div(struct lpc18xx_clk_branch *bran
|
|||
div->width = 1;
|
||||
|
||||
div_hw = &div->hw;
|
||||
div_ops = &clk_divider_ops;
|
||||
div_ops = &clk_divider_ro_ops;
|
||||
}
|
||||
|
||||
branch->gate.reg = branch->offset + reg_base;
|
||||
|
|
|
@ -90,7 +90,9 @@ static struct clk *rockchip_clk_register_branch(const char *name,
|
|||
div->width = div_width;
|
||||
div->lock = lock;
|
||||
div->table = div_table;
|
||||
div_ops = &clk_divider_ops;
|
||||
div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
|
||||
? &clk_divider_ro_ops
|
||||
: &clk_divider_ops;
|
||||
}
|
||||
|
||||
clk = clk_register_composite(NULL, name, parent_names, num_parents,
|
||||
|
|
|
@ -1,9 +1,17 @@
|
|||
# Recent Exynos platforms should just select COMMON_CLK_SAMSUNG:
|
||||
config COMMON_CLK_SAMSUNG
|
||||
bool
|
||||
select COMMON_CLK
|
||||
bool "Samsung Exynos clock controller support" if COMPILE_TEST
|
||||
# Clocks on ARM64 SoCs (e.g. Exynos5433, Exynos7) are chosen by
|
||||
# EXYNOS_ARM64_COMMON_CLK to avoid building them on ARMv7:
|
||||
select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
|
||||
|
||||
config EXYNOS_ARM64_COMMON_CLK
|
||||
bool "Samsung Exynos ARMv8-family clock controller support" if COMPILE_TEST
|
||||
depends on COMMON_CLK_SAMSUNG
|
||||
|
||||
# For S3C24XX platforms, select following symbols:
|
||||
config S3C2410_COMMON_CLK
|
||||
bool
|
||||
bool "Samsung S3C2410 clock controller support" if COMPILE_TEST
|
||||
select COMMON_CLK_SAMSUNG
|
||||
help
|
||||
Build the s3c2410 clock driver based on the common clock framework.
|
||||
|
@ -17,10 +25,9 @@ config S3C2410_COMMON_DCLK
|
|||
framework.
|
||||
|
||||
config S3C2412_COMMON_CLK
|
||||
bool
|
||||
bool "Samsung S3C2412 clock controller support" if COMPILE_TEST
|
||||
select COMMON_CLK_SAMSUNG
|
||||
|
||||
config S3C2443_COMMON_CLK
|
||||
bool
|
||||
bool "Samsung S3C2443 clock controller support" if COMPILE_TEST
|
||||
select COMMON_CLK_SAMSUNG
|
||||
|
||||
|
|
|
@ -10,11 +10,11 @@ obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
|
|||
obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o
|
||||
obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
|
||||
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos5433.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o
|
||||
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS7) += clk-exynos7.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
|
||||
obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
|
||||
obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
|
||||
obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
|
||||
|
|
|
@ -822,11 +822,10 @@ err:
|
|||
if (!clk_data->clks[i])
|
||||
continue;
|
||||
|
||||
composite = container_of(__clk_get_hw(clk_data->clks[i]),
|
||||
struct clk_composite, hw);
|
||||
kfree(container_of(composite->gate_hw, struct clk_gate, hw));
|
||||
kfree(container_of(composite->rate_hw, struct clk_divider, hw));
|
||||
kfree(container_of(composite->mux_hw, struct clk_mux, hw));
|
||||
composite = to_clk_composite(__clk_get_hw(clk_data->clks[i]));
|
||||
kfree(to_clk_gate(composite->gate_hw));
|
||||
kfree(to_clk_divider(composite->rate_hw));
|
||||
kfree(to_clk_mux(composite->mux_hw));
|
||||
}
|
||||
|
||||
kfree(clk_data->clks);
|
||||
|
|
|
@ -28,8 +28,6 @@
|
|||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
||||
#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
|
||||
|
||||
static unsigned long ti_composite_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
|
|
|
@ -26,8 +26,6 @@
|
|||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
||||
#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
|
||||
|
||||
#define div_mask(d) ((1 << ((d)->width)) - 1)
|
||||
|
||||
static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
|
||||
|
|
|
@ -24,8 +24,6 @@
|
|||
|
||||
#include "clock.h"
|
||||
|
||||
#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
|
||||
|
||||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
||||
|
|
|
@ -26,8 +26,6 @@
|
|||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
||||
#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
|
||||
|
||||
static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_mux *mux = to_clk_mux(hw);
|
||||
|
|
|
@ -276,6 +276,8 @@ struct clk_fixed_rate {
|
|||
u8 flags;
|
||||
};
|
||||
|
||||
#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
|
||||
|
||||
extern const struct clk_ops clk_fixed_rate_ops;
|
||||
struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
|
@ -314,6 +316,8 @@ struct clk_gate {
|
|||
spinlock_t *lock;
|
||||
};
|
||||
|
||||
#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
|
||||
|
||||
#define CLK_GATE_SET_TO_DISABLE BIT(0)
|
||||
#define CLK_GATE_HIWORD_MASK BIT(1)
|
||||
|
||||
|
@ -376,6 +380,8 @@ struct clk_divider {
|
|||
spinlock_t *lock;
|
||||
};
|
||||
|
||||
#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
|
||||
|
||||
#define CLK_DIVIDER_ONE_BASED BIT(0)
|
||||
#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
|
||||
#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
|
||||
|
@ -385,6 +391,7 @@ struct clk_divider {
|
|||
#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
|
||||
|
||||
extern const struct clk_ops clk_divider_ops;
|
||||
extern const struct clk_ops clk_divider_ro_ops;
|
||||
|
||||
unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
|
||||
unsigned int val, const struct clk_div_table *table,
|
||||
|
@ -440,6 +447,8 @@ struct clk_mux {
|
|||
spinlock_t *lock;
|
||||
};
|
||||
|
||||
#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
|
||||
|
||||
#define CLK_MUX_INDEX_ONE BIT(0)
|
||||
#define CLK_MUX_INDEX_BIT BIT(1)
|
||||
#define CLK_MUX_HIWORD_MASK BIT(2)
|
||||
|
@ -483,6 +492,8 @@ struct clk_fixed_factor {
|
|||
unsigned int div;
|
||||
};
|
||||
|
||||
#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
|
||||
|
||||
extern const struct clk_ops clk_fixed_factor_ops;
|
||||
struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
|
@ -514,6 +525,8 @@ struct clk_fractional_divider {
|
|||
spinlock_t *lock;
|
||||
};
|
||||
|
||||
#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
|
||||
|
||||
extern const struct clk_ops clk_fractional_divider_ops;
|
||||
struct clk *clk_register_fractional_divider(struct device *dev,
|
||||
const char *name, const char *parent_name, unsigned long flags,
|
||||
|
@ -550,6 +563,8 @@ struct clk_multiplier {
|
|||
spinlock_t *lock;
|
||||
};
|
||||
|
||||
#define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
|
||||
|
||||
#define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
|
||||
#define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
|
||||
|
||||
|
@ -579,6 +594,8 @@ struct clk_composite {
|
|||
const struct clk_ops *gate_ops;
|
||||
};
|
||||
|
||||
#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
|
||||
|
||||
struct clk *clk_register_composite(struct device *dev, const char *name,
|
||||
const char * const *parent_names, int num_parents,
|
||||
struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
|
||||
|
@ -601,6 +618,8 @@ struct clk_gpio {
|
|||
struct gpio_desc *gpiod;
|
||||
};
|
||||
|
||||
#define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw)
|
||||
|
||||
extern const struct clk_ops clk_gpio_gate_ops;
|
||||
struct clk *clk_register_gpio_gate(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned gpio, bool active_low,
|
||||
|
|
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