powerpc fixes for 5.7 #5
A revert of a recent change to the PTE bits for 32-bit BookS, which broke swap. And a "fix" to disable STRICT_KERNEL_RWX for 64-bit in Kconfig, as it's causing crashes for some people. Thanks to: Christophe Leroy, Rui Salvaterra. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEJFGtCPCthwEv2Y/bUevqPMjhpYAFAl7H1aMTHG1wZUBlbGxl cm1hbi5pZC5hdQAKCRBR6+o8yOGlgG3sD/9L72cw3cI2TcDTw+OEv2S2TyXrZZc3 09WyUeerEv8mK8pk1eH8jVk6BqQK9bVZaq/3zYxLr5vnL1m+CZ4Qr8eGy5AcV3AC HXiGKhLbEh4btuoN3NwJ6fvEzA85dMTWsowGpgW8JgX1o7rtJmro0XW9EndhZGd2 WWMBDsWo+RaKODej0c0Bz3TAOVgvxalE1SSLq63Q1sRoPhAZAJ0l8K3ED/EgC+tb v/VUi3fQNJngIzlMBc0sNOPp7NgcnDXoozAkW5c2Bp7YURbzeU0oXmsMAxQnyzee MP4MY1fAHI3CYdQ7QVRRDpQsTc84bAXVD+te+zhUJejaNm3mWLojRVieYT98eZXi iCi4Q0aSuAh3H8rxaYgi9ZemUkSKn+5pLu4kIAyMkBtnTB50E1YqUXVxfPcqk48N Y3Fkd6AyZ2/HyxS3bBVAubT/+GxK8HgQNGUBaF7iS50QKd6fl8EKjEBK1tVbYrTj xH7lXJpBnLCIj2ygZE1mBLxG8UTLGTfdnpxVNfVkNsLZK4tdsMaQ/llOzVA1uBOY twaRAhJkC0RHKHak1KNIQ8gh6HPjqwfg+P6SXHvT347YlTbsKgZei9wHtnZy4lsD CAnSImfgJMbzXCoULSoQbgXW0PloRZ1Zz1+WdfxmNjcNsRSqBNoaS1CaPKr7f8to a5JEWrUY1D49YQ== =yBu+ -----END PGP SIGNATURE----- Merge tag 'powerpc-5.7-5' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux Pull powerpc fixes from Michael Ellerman: - a revert of a recent change to the PTE bits for 32-bit BookS, which broke swap. - a "fix" to disable STRICT_KERNEL_RWX for 64-bit in Kconfig, as it's causing crashes for some people. Thanks to Christophe Leroy and Rui Salvaterra. * tag 'powerpc-5.7-5' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: powerpc/64s: Disable STRICT_KERNEL_RWX Revert "powerpc/32s: reorder Linux PTE bits to better match Hash PTE bits."
This commit is contained in:
Linus Torvalds
Коммит
c8347bbf19
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@ -130,7 +130,7 @@ config PPC
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select ARCH_HAS_PTE_SPECIAL
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select ARCH_HAS_MEMBARRIER_CALLBACKS
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select ARCH_HAS_SCALED_CPUTIME if VIRT_CPU_ACCOUNTING_NATIVE && PPC_BOOK3S_64
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select ARCH_HAS_STRICT_KERNEL_RWX if ((PPC_BOOK3S_64 || PPC32) && !HIBERNATION)
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select ARCH_HAS_STRICT_KERNEL_RWX if (PPC32 && !HIBERNATION)
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select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
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select ARCH_HAS_UACCESS_FLUSHCACHE
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select ARCH_HAS_UACCESS_MCSAFE if PPC64
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@ -17,9 +17,9 @@
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* updating the accessed and modified bits in the page table tree.
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*/
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#define _PAGE_USER 0x001 /* usermode access allowed */
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#define _PAGE_RW 0x002 /* software: user write access allowed */
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#define _PAGE_PRESENT 0x004 /* software: pte contains a translation */
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#define _PAGE_PRESENT 0x001 /* software: pte contains a translation */
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#define _PAGE_HASHPTE 0x002 /* hash_page has made an HPTE for this pte */
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#define _PAGE_USER 0x004 /* usermode access allowed */
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#define _PAGE_GUARDED 0x008 /* G: prohibit speculative access */
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#define _PAGE_COHERENT 0x010 /* M: enforce memory coherence (SMP systems) */
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#define _PAGE_NO_CACHE 0x020 /* I: cache inhibit */
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@ -27,7 +27,7 @@
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#define _PAGE_DIRTY 0x080 /* C: page changed */
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#define _PAGE_ACCESSED 0x100 /* R: page referenced */
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#define _PAGE_EXEC 0x200 /* software: exec allowed */
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#define _PAGE_HASHPTE 0x400 /* hash_page has made an HPTE for this pte */
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#define _PAGE_RW 0x400 /* software: user write access allowed */
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#define _PAGE_SPECIAL 0x800 /* software: Special page */
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#ifdef CONFIG_PTE_64BIT
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@ -348,7 +348,7 @@ BEGIN_MMU_FTR_SECTION
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andis. r0, r5, (DSISR_BAD_FAULT_32S | DSISR_DABRMATCH)@h
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#endif
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bne handle_page_fault_tramp_2 /* if not, try to put a PTE */
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rlwinm r3, r5, 32 - 24, 30, 30 /* DSISR_STORE -> _PAGE_RW */
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rlwinm r3, r5, 32 - 15, 21, 21 /* DSISR_STORE -> _PAGE_RW */
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bl hash_page
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b handle_page_fault_tramp_1
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FTR_SECTION_ELSE
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@ -497,6 +497,7 @@ InstructionTLBMiss:
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andc. r1,r1,r0 /* check access & ~permission */
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bne- InstructionAddressInvalid /* return if access not permitted */
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/* Convert linux-style PTE to low word of PPC-style PTE */
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rlwimi r0,r0,32-2,31,31 /* _PAGE_USER -> PP lsb */
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ori r1, r1, 0xe06 /* clear out reserved bits */
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andc r1, r0, r1 /* PP = user? 1 : 0 */
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BEGIN_FTR_SECTION
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@ -564,8 +565,9 @@ DataLoadTLBMiss:
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* we would need to update the pte atomically with lwarx/stwcx.
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*/
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/* Convert linux-style PTE to low word of PPC-style PTE */
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rlwinm r1,r0,0,30,30 /* _PAGE_RW -> PP msb */
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rlwimi r0,r0,1,30,30 /* _PAGE_USER -> PP msb */
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rlwinm r1,r0,32-9,30,30 /* _PAGE_RW -> PP msb */
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rlwimi r0,r0,32-1,30,30 /* _PAGE_USER -> PP msb */
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rlwimi r0,r0,32-1,31,31 /* _PAGE_USER -> PP lsb */
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ori r1,r1,0xe04 /* clear out reserved bits */
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andc r1,r0,r1 /* PP = user? rw? 1: 3: 0 */
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BEGIN_FTR_SECTION
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@ -643,6 +645,7 @@ DataStoreTLBMiss:
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* we would need to update the pte atomically with lwarx/stwcx.
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*/
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/* Convert linux-style PTE to low word of PPC-style PTE */
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rlwimi r0,r0,32-2,31,31 /* _PAGE_USER -> PP lsb */
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li r1,0xe06 /* clear out reserved bits & PP msb */
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andc r1,r0,r1 /* PP = user? 1: 0 */
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BEGIN_FTR_SECTION
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@ -35,7 +35,7 @@ mmu_hash_lock:
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/*
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* Load a PTE into the hash table, if possible.
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* The address is in r4, and r3 contains an access flag:
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* _PAGE_RW (0x002) if a write.
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* _PAGE_RW (0x400) if a write.
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* r9 contains the SRR1 value, from which we use the MSR_PR bit.
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* SPRG_THREAD contains the physical address of the current task's thread.
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*
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@ -69,7 +69,7 @@ _GLOBAL(hash_page)
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blt+ 112f /* assume user more likely */
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lis r5, (swapper_pg_dir - PAGE_OFFSET)@ha /* if kernel address, use */
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addi r5 ,r5 ,(swapper_pg_dir - PAGE_OFFSET)@l /* kernel page table */
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rlwimi r3,r9,32-14,31,31 /* MSR_PR -> _PAGE_USER */
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rlwimi r3,r9,32-12,29,29 /* MSR_PR -> _PAGE_USER */
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112:
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#ifndef CONFIG_PTE_64BIT
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rlwimi r5,r4,12,20,29 /* insert top 10 bits of address */
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@ -94,7 +94,7 @@ _GLOBAL(hash_page)
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#else
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rlwimi r8,r4,23,20,28 /* compute pte address */
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#endif
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rlwinm r0,r3,6,24,24 /* _PAGE_RW access -> _PAGE_DIRTY */
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rlwinm r0,r3,32-3,24,24 /* _PAGE_RW access -> _PAGE_DIRTY */
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ori r0,r0,_PAGE_ACCESSED|_PAGE_HASHPTE
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/*
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@ -310,9 +310,11 @@ Hash_msk = (((1 << Hash_bits) - 1) * 64)
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_GLOBAL(create_hpte)
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/* Convert linux-style PTE (r5) to low word of PPC-style PTE (r8) */
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rlwinm r8,r5,32-9,30,30 /* _PAGE_RW -> PP msb */
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rlwinm r0,r5,32-6,30,30 /* _PAGE_DIRTY -> PP msb */
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and r8,r5,r0 /* writable if _RW & _DIRTY */
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rlwimi r5,r5,1,30,30 /* _PAGE_USER -> PP msb */
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and r8,r8,r0 /* writable if _RW & _DIRTY */
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rlwimi r5,r5,32-1,30,30 /* _PAGE_USER -> PP msb */
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rlwimi r5,r5,32-2,31,31 /* _PAGE_USER -> PP lsb */
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ori r8,r8,0xe04 /* clear out reserved bits */
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andc r8,r5,r8 /* PP = user? (rw&dirty? 1: 3): 0 */
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BEGIN_FTR_SECTION
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@ -564,7 +566,7 @@ _GLOBAL(flush_hash_pages)
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33: lwarx r8,0,r5 /* fetch the pte flags word */
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andi. r0,r8,_PAGE_HASHPTE
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beq 8f /* done if HASHPTE is already clear */
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rlwinm r8,r8,0,~_PAGE_HASHPTE /* clear HASHPTE bit */
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rlwinm r8,r8,0,31,29 /* clear HASHPTE bit */
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stwcx. r8,0,r5 /* update the pte */
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bne- 33b
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