drm/i915: Remove ddi_pll_sel from intel_crtc_state
The value of ddi_pll_sel is derived from the selection of shared dpll, so just calculate the final value when necessary. v2: Actually remove it from crtc state and delete remaining usages. (CI) Reviewed-by: Durgadoss R <durgadoss.r@intel.com> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
This commit is contained in:
Ander Conselvan de Oliveira
Rodrigo Vivi
Родитель
dfa1048035
Коммит
c856052abc
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@ -546,6 +546,27 @@ static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
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DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
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}
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static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll)
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{
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switch (pll->id) {
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case DPLL_ID_WRPLL1:
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return PORT_CLK_SEL_WRPLL1;
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case DPLL_ID_WRPLL2:
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return PORT_CLK_SEL_WRPLL2;
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case DPLL_ID_SPLL:
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return PORT_CLK_SEL_SPLL;
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case DPLL_ID_LCPLL_810:
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return PORT_CLK_SEL_LCPLL_810;
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case DPLL_ID_LCPLL_1350:
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return PORT_CLK_SEL_LCPLL_1350;
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case DPLL_ID_LCPLL_2700:
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return PORT_CLK_SEL_LCPLL_2700;
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default:
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MISSING_CASE(pll->id);
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return PORT_CLK_SEL_NONE;
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}
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}
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/* Starting with Haswell, different DDI ports can work in FDI mode for
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* connection to the PCH-located connectors. For this, it is necessary to train
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* both the DDI port and PCH receiver for the desired DDI buffer settings.
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@ -561,7 +582,7 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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struct intel_encoder *encoder;
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u32 temp, i, rx_ctl_val;
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u32 temp, i, rx_ctl_val, ddi_pll_sel;
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for_each_encoder_on_crtc(dev, crtc, encoder) {
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WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
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@ -592,8 +613,9 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
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I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
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/* Configure Port Clock Select */
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I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
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WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
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ddi_pll_sel = hsw_pll_to_ddi_pll_sel(intel_crtc->config->shared_dpll);
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I915_WRITE(PORT_CLK_SEL(PORT_E), ddi_pll_sel);
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WARN_ON(ddi_pll_sel != PORT_CLK_SEL_SPLL);
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/* Start the training iterating through available voltages and emphasis,
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* testing each value twice. */
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@ -870,7 +892,7 @@ static void skl_ddi_clock_get(struct intel_encoder *encoder,
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int link_clock = 0;
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uint32_t dpll_ctl1, dpll;
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dpll = pipe_config->ddi_pll_sel;
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dpll = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll);
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dpll_ctl1 = I915_READ(DPLL_CTRL1);
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@ -918,7 +940,7 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder,
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int link_clock = 0;
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u32 val, pll;
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val = pipe_config->ddi_pll_sel;
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val = hsw_pll_to_ddi_pll_sel(pipe_config->shared_dpll);
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switch (val & PORT_CLK_SEL_MASK) {
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case PORT_CLK_SEL_LCPLL_810:
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link_clock = 81000;
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@ -1586,13 +1608,15 @@ uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
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}
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void intel_ddi_clk_select(struct intel_encoder *encoder,
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const struct intel_crtc_state *pipe_config)
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struct intel_shared_dpll *pll)
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{
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struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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enum port port = intel_ddi_get_encoder_port(encoder);
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if (WARN_ON(!pll))
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return;
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if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
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uint32_t dpll = pipe_config->ddi_pll_sel;
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uint32_t val;
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/* DDI -> PLL mapping */
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@ -1600,14 +1624,13 @@ void intel_ddi_clk_select(struct intel_encoder *encoder,
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val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
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DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
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val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
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val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->id, port) |
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DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
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I915_WRITE(DPLL_CTRL2, val);
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} else if (INTEL_INFO(dev_priv)->gen < 9) {
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WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE);
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I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel);
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I915_WRITE(PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
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}
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}
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@ -1632,7 +1655,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder,
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intel_edp_panel_on(intel_dp);
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}
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intel_ddi_clk_select(intel_encoder, crtc->config);
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intel_ddi_clk_select(intel_encoder, crtc->config->shared_dpll);
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if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
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struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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@ -10435,15 +10435,12 @@ static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
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switch (port) {
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case PORT_A:
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pipe_config->ddi_pll_sel = SKL_DPLL0;
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id = DPLL_ID_SKL_DPLL0;
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break;
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case PORT_B:
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pipe_config->ddi_pll_sel = SKL_DPLL1;
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id = DPLL_ID_SKL_DPLL1;
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break;
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case PORT_C:
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pipe_config->ddi_pll_sel = SKL_DPLL2;
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id = DPLL_ID_SKL_DPLL2;
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break;
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default:
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@ -10462,25 +10459,10 @@ static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
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u32 temp;
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temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
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pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
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id = temp >> (port * 3 + 1);
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switch (pipe_config->ddi_pll_sel) {
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case SKL_DPLL0:
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id = DPLL_ID_SKL_DPLL0;
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break;
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case SKL_DPLL1:
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id = DPLL_ID_SKL_DPLL1;
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break;
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case SKL_DPLL2:
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id = DPLL_ID_SKL_DPLL2;
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break;
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case SKL_DPLL3:
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id = DPLL_ID_SKL_DPLL3;
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break;
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default:
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MISSING_CASE(pipe_config->ddi_pll_sel);
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if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
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return;
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}
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pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
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}
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@ -10490,10 +10472,9 @@ static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
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struct intel_crtc_state *pipe_config)
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{
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enum intel_dpll_id id;
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uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
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pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
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switch (pipe_config->ddi_pll_sel) {
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switch (ddi_pll_sel) {
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case PORT_CLK_SEL_WRPLL1:
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id = DPLL_ID_WRPLL1;
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break;
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@ -10513,7 +10494,7 @@ static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
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id = DPLL_ID_LCPLL_2700;
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break;
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default:
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MISSING_CASE(pipe_config->ddi_pll_sel);
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MISSING_CASE(ddi_pll_sel);
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/* fall through */
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case PORT_CLK_SEL_NONE:
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return;
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@ -12797,10 +12778,9 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
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DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
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if (IS_BROXTON(dev)) {
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DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
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DRM_DEBUG_KMS("dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
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"pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
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"pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
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pipe_config->ddi_pll_sel,
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pipe_config->dpll_hw_state.ebb0,
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pipe_config->dpll_hw_state.ebb4,
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pipe_config->dpll_hw_state.pll0,
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@ -12813,15 +12793,13 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
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pipe_config->dpll_hw_state.pll10,
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pipe_config->dpll_hw_state.pcsdw12);
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} else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
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DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
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DRM_DEBUG_KMS("dpll_hw_state: "
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"ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
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pipe_config->ddi_pll_sel,
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pipe_config->dpll_hw_state.ctrl1,
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pipe_config->dpll_hw_state.cfgcr1,
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pipe_config->dpll_hw_state.cfgcr2);
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} else if (HAS_DDI(dev)) {
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DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
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pipe_config->ddi_pll_sel,
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DRM_DEBUG_KMS("dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
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pipe_config->dpll_hw_state.wrpll,
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pipe_config->dpll_hw_state.spll);
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} else {
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@ -12930,7 +12908,6 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
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struct intel_crtc_scaler_state scaler_state;
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struct intel_dpll_hw_state dpll_hw_state;
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struct intel_shared_dpll *shared_dpll;
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uint32_t ddi_pll_sel;
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bool force_thru;
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/* FIXME: before the switch to atomic started, a new pipe_config was
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@ -12942,7 +12919,6 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
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scaler_state = crtc_state->scaler_state;
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shared_dpll = crtc_state->shared_dpll;
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dpll_hw_state = crtc_state->dpll_hw_state;
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ddi_pll_sel = crtc_state->ddi_pll_sel;
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force_thru = crtc_state->pch_pfit.force_thru;
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memset(crtc_state, 0, sizeof *crtc_state);
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@ -12951,7 +12927,6 @@ clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
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crtc_state->scaler_state = scaler_state;
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crtc_state->shared_dpll = shared_dpll;
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crtc_state->dpll_hw_state = dpll_hw_state;
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crtc_state->ddi_pll_sel = ddi_pll_sel;
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crtc_state->pch_pfit.force_thru = force_thru;
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}
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@ -13374,8 +13349,6 @@ intel_pipe_config_compare(struct drm_device *dev,
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PIPE_CONF_CHECK_I(double_wide);
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PIPE_CONF_CHECK_X(ddi_pll_sel);
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PIPE_CONF_CHECK_P(shared_dpll);
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PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
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PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
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@ -150,7 +150,8 @@ static void intel_mst_pre_enable_dp(struct intel_encoder *encoder,
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DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links);
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if (intel_dp->active_mst_links == 0) {
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intel_ddi_clk_select(&intel_dig_port->base, pipe_config);
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intel_ddi_clk_select(&intel_dig_port->base,
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pipe_config->shared_dpll);
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intel_prepare_dp_ddi_buffers(&intel_dig_port->base);
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intel_dp_set_link_params(intel_dp,
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@ -452,26 +452,6 @@ static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
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return val & SPLL_PLL_ENABLE;
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}
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static uint32_t hsw_pll_to_ddi_pll_sel(struct intel_shared_dpll *pll)
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{
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switch (pll->id) {
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case DPLL_ID_WRPLL1:
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return PORT_CLK_SEL_WRPLL1;
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case DPLL_ID_WRPLL2:
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return PORT_CLK_SEL_WRPLL2;
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case DPLL_ID_SPLL:
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return PORT_CLK_SEL_SPLL;
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case DPLL_ID_LCPLL_810:
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return PORT_CLK_SEL_LCPLL_810;
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case DPLL_ID_LCPLL_1350:
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return PORT_CLK_SEL_LCPLL_1350;
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case DPLL_ID_LCPLL_2700:
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return PORT_CLK_SEL_LCPLL_2700;
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default:
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return PORT_CLK_SEL_NONE;
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}
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}
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#define LC_FREQ 2700
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#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
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@ -751,8 +731,6 @@ hsw_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
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if (!pll)
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return NULL;
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crtc_state->ddi_pll_sel = hsw_pll_to_ddi_pll_sel(pll);
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intel_reference_shared_dpll(pll, crtc_state);
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return pll;
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@ -1274,8 +1252,6 @@ skl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
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if (!pll)
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return NULL;
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crtc_state->ddi_pll_sel = pll->id;
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intel_reference_shared_dpll(pll, crtc_state);
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return pll;
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@ -1628,9 +1604,6 @@ bxt_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
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intel_reference_shared_dpll(pll, crtc_state);
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/* shared DPLL id 0 is DPLL A */
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crtc_state->ddi_pll_sel = pll->id;
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return pll;
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}
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@ -590,12 +590,6 @@ struct intel_crtc_state {
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/* Selected dpll when shared or NULL. */
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struct intel_shared_dpll *shared_dpll;
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/*
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* - PORT_CLK_SEL for DDI ports on HSW/BDW.
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* - enum skl_dpll on SKL
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*/
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uint32_t ddi_pll_sel;
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/* Actual register state of the dpll, for shared dpll cross-checking. */
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struct intel_dpll_hw_state dpll_hw_state;
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@ -1136,7 +1130,7 @@ void intel_crt_reset(struct drm_encoder *encoder);
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/* intel_ddi.c */
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void intel_ddi_clk_select(struct intel_encoder *encoder,
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const struct intel_crtc_state *pipe_config);
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struct intel_shared_dpll *pll);
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void intel_ddi_fdi_post_disable(struct intel_encoder *intel_encoder,
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struct intel_crtc_state *old_crtc_state,
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struct drm_connector_state *old_conn_state);
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