drm/vc4: hdmi: Enable the scrambler
The HDMI controller on the BCM2711 includes a scrambler in order to reach the HDMI 2.0 modes that require it. Let's add the support for it. Acked-by: Thomas Zimmermann <tzimmermann@suse.de> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210507150515.257424-11-maxime@cerno.tech
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@ -35,6 +35,7 @@
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#include <drm/drm_edid.h>
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#include <drm/drm_probe_helper.h>
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#include <drm/drm_simple_kms_helper.h>
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#include <drm/drm_scdc_helper.h>
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/i2c.h>
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@ -76,6 +77,8 @@
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#define VC5_HDMI_VERTB_VSPO_SHIFT 16
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#define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
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#define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0)
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#define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8
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#define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8)
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@ -518,6 +521,64 @@ static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
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vc4_hdmi_set_hdr_infoframe(encoder);
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}
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static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
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struct drm_display_mode *mode)
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{
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struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
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struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
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struct drm_display_info *display = &vc4_hdmi->connector.display_info;
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if (!vc4_encoder->hdmi_monitor)
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return false;
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if (!display->hdmi.scdc.supported ||
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!display->hdmi.scdc.scrambling.supported)
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return false;
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return true;
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}
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static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
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{
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struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
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struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
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if (!vc4_hdmi_supports_scrambling(encoder, mode))
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return;
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if (!vc4_hdmi_mode_needs_scrambling(mode))
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return;
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drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
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drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
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HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
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VC5_HDMI_SCRAMBLER_CTL_ENABLE);
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}
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static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
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{
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struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
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struct drm_crtc *crtc = encoder->crtc;
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/*
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* At boot, encoder->crtc will be NULL. Since we don't know the
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* state of the scrambler and in order to avoid any
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* inconsistency, let's disable it all the time.
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*/
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if (crtc && !vc4_hdmi_supports_scrambling(encoder, &crtc->mode))
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return;
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if (crtc && !vc4_hdmi_mode_needs_scrambling(&crtc->mode))
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return;
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HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
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~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
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drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
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drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
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}
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static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
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struct drm_atomic_state *state)
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{
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@ -530,6 +591,8 @@ static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
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HDMI_WRITE(HDMI_VID_CTL,
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HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
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vc4_hdmi_disable_scrambling(encoder);
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}
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static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
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@ -980,6 +1043,7 @@ static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
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}
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vc4_hdmi_recenter_fifo(vc4_hdmi);
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vc4_hdmi_enable_scrambling(encoder);
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}
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static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
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@ -100,6 +100,7 @@ enum vc4_hdmi_field {
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HDMI_RM_FORMAT,
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HDMI_RM_OFFSET,
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HDMI_SCHEDULER_CONTROL,
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HDMI_SCRAMBLER_CTL,
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HDMI_SW_RESET_CONTROL,
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HDMI_TX_PHY_CHANNEL_SWAP,
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HDMI_TX_PHY_CLK_DIV,
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@ -238,6 +239,7 @@ static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi0_fields[] = {
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VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178),
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VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c),
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VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),
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VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4),
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VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
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VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),
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@ -317,6 +319,7 @@ static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi1_fields[] = {
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VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178),
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VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c),
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VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),
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VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4),
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VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
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VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),
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