Pull hp-machvec into release branch
This commit is contained in:
Tony Luck
Коммит
c85749e6d1
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@ -17,7 +17,7 @@
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#include <asm/machvec.h>
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/* swiotlb declarations & definitions: */
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extern void swiotlb_init_with_default_size (size_t size);
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extern int swiotlb_late_init_with_default_size (size_t size);
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extern ia64_mv_dma_alloc_coherent swiotlb_alloc_coherent;
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extern ia64_mv_dma_free_coherent swiotlb_free_coherent;
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extern ia64_mv_dma_map_single swiotlb_map_single;
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@ -67,7 +67,16 @@ void
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hwsw_init (void)
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{
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/* default to a smallish 2MB sw I/O TLB */
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swiotlb_init_with_default_size (2 * (1<<20));
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if (swiotlb_late_init_with_default_size (2 * (1<<20)) != 0) {
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#ifdef CONFIG_IA64_GENERIC
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/* Better to have normal DMA than panic */
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printk(KERN_WARNING "%s: Failed to initialize software I/O TLB,"
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" reverting to hpzx1 platform vector\n", __FUNCTION__);
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machvec_init("hpzx1");
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#else
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panic("Unable to initialize software I/O TLB services");
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#endif
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}
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}
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void *
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@ -2028,10 +2028,41 @@ static struct acpi_driver acpi_sba_ioc_driver = {
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static int __init
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sba_init(void)
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{
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acpi_bus_register_driver(&acpi_sba_ioc_driver);
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if (!ioc_list)
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if (!ia64_platform_is("hpzx1") && !ia64_platform_is("hpzx1_swiotlb"))
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return 0;
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acpi_bus_register_driver(&acpi_sba_ioc_driver);
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if (!ioc_list) {
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#ifdef CONFIG_IA64_GENERIC
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extern int swiotlb_late_init_with_default_size (size_t size);
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/*
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* If we didn't find something sba_iommu can claim, we
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* need to setup the swiotlb and switch to the dig machvec.
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*/
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if (swiotlb_late_init_with_default_size(64 * (1<<20)) != 0)
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panic("Unable to find SBA IOMMU or initialize "
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"software I/O TLB: Try machvec=dig boot option");
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machvec_init("dig");
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#else
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panic("Unable to find SBA IOMMU: Try a generic or DIG kernel");
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#endif
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return 0;
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}
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#if defined(CONFIG_IA64_GENERIC) || defined(CONFIG_IA64_HP_ZX1_SWIOTLB)
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/*
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* hpzx1_swiotlb needs to have a fairly small swiotlb bounce
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* buffer setup to support devices with smaller DMA masks than
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* sba_iommu can handle.
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*/
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if (ia64_platform_is("hpzx1_swiotlb")) {
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extern void hwsw_init(void);
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hwsw_init();
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}
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#endif
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#ifdef CONFIG_PCI
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{
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struct pci_bus *b = NULL;
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@ -2048,18 +2079,6 @@ sba_init(void)
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subsys_initcall(sba_init); /* must be initialized after ACPI etc., but before any drivers... */
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extern void dig_setup(char**);
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/*
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* MAX_DMA_ADDRESS needs to be setup prior to paging_init to do any good,
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* so we use the platform_setup hook to fix it up.
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*/
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void __init
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sba_setup(char **cmdline_p)
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{
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MAX_DMA_ADDRESS = ~0UL;
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dig_setup(cmdline_p);
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}
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static int __init
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nosbagart(char *str)
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{
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@ -49,6 +49,15 @@
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*/
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#define IO_TLB_SHIFT 11
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#define SLABS_PER_PAGE (1 << (PAGE_SHIFT - IO_TLB_SHIFT))
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/*
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* Minimum IO TLB size to bother booting with. Systems with mainly
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* 64bit capable cards will only lightly use the swiotlb. If we can't
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* allocate a contiguous 1MB, we're probably in trouble anyway.
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*/
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#define IO_TLB_MIN_SLABS ((1<<20) >> IO_TLB_SHIFT)
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int swiotlb_force;
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/*
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@ -154,6 +163,99 @@ swiotlb_init (void)
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swiotlb_init_with_default_size(64 * (1<<20)); /* default to 64MB */
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}
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/*
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* Systems with larger DMA zones (those that don't support ISA) can
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* initialize the swiotlb later using the slab allocator if needed.
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* This should be just like above, but with some error catching.
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*/
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int
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swiotlb_late_init_with_default_size (size_t default_size)
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{
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unsigned long i, req_nslabs = io_tlb_nslabs;
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unsigned int order;
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if (!io_tlb_nslabs) {
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io_tlb_nslabs = (default_size >> IO_TLB_SHIFT);
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io_tlb_nslabs = ALIGN(io_tlb_nslabs, IO_TLB_SEGSIZE);
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}
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/*
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* Get IO TLB memory from the low pages
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*/
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order = get_order(io_tlb_nslabs * (1 << IO_TLB_SHIFT));
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io_tlb_nslabs = SLABS_PER_PAGE << order;
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while ((SLABS_PER_PAGE << order) > IO_TLB_MIN_SLABS) {
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io_tlb_start = (char *)__get_free_pages(GFP_DMA | __GFP_NOWARN,
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order);
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if (io_tlb_start)
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break;
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order--;
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}
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if (!io_tlb_start)
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goto cleanup1;
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if (order != get_order(io_tlb_nslabs * (1 << IO_TLB_SHIFT))) {
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printk(KERN_WARNING "Warning: only able to allocate %ld MB "
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"for software IO TLB\n", (PAGE_SIZE << order) >> 20);
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io_tlb_nslabs = SLABS_PER_PAGE << order;
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}
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io_tlb_end = io_tlb_start + io_tlb_nslabs * (1 << IO_TLB_SHIFT);
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memset(io_tlb_start, 0, io_tlb_nslabs * (1 << IO_TLB_SHIFT));
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/*
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* Allocate and initialize the free list array. This array is used
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* to find contiguous free memory regions of size up to IO_TLB_SEGSIZE
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* between io_tlb_start and io_tlb_end.
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*/
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io_tlb_list = (unsigned int *)__get_free_pages(GFP_KERNEL,
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get_order(io_tlb_nslabs * sizeof(int)));
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if (!io_tlb_list)
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goto cleanup2;
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for (i = 0; i < io_tlb_nslabs; i++)
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io_tlb_list[i] = IO_TLB_SEGSIZE - OFFSET(i, IO_TLB_SEGSIZE);
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io_tlb_index = 0;
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io_tlb_orig_addr = (unsigned char **)__get_free_pages(GFP_KERNEL,
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get_order(io_tlb_nslabs * sizeof(char *)));
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if (!io_tlb_orig_addr)
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goto cleanup3;
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memset(io_tlb_orig_addr, 0, io_tlb_nslabs * sizeof(char *));
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/*
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* Get the overflow emergency buffer
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*/
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io_tlb_overflow_buffer = (void *)__get_free_pages(GFP_DMA,
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get_order(io_tlb_overflow));
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if (!io_tlb_overflow_buffer)
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goto cleanup4;
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printk(KERN_INFO "Placing %ldMB software IO TLB between 0x%lx - "
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"0x%lx\n", (io_tlb_nslabs * (1 << IO_TLB_SHIFT)) >> 20,
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virt_to_phys(io_tlb_start), virt_to_phys(io_tlb_end));
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return 0;
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cleanup4:
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free_pages((unsigned long)io_tlb_orig_addr, get_order(io_tlb_nslabs *
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sizeof(char *)));
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io_tlb_orig_addr = NULL;
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cleanup3:
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free_pages((unsigned long)io_tlb_list, get_order(io_tlb_nslabs *
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sizeof(int)));
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io_tlb_list = NULL;
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io_tlb_end = NULL;
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cleanup2:
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free_pages((unsigned long)io_tlb_start, order);
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io_tlb_start = NULL;
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cleanup1:
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io_tlb_nslabs = req_nslabs;
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return -ENOMEM;
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}
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static inline int
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address_needs_mapping(struct device *hwdev, dma_addr_t addr)
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{
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@ -1,8 +1,7 @@
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#ifndef _ASM_IA64_MACHVEC_HPZX1_h
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#define _ASM_IA64_MACHVEC_HPZX1_h
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extern ia64_mv_setup_t dig_setup;
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extern ia64_mv_setup_t sba_setup;
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extern ia64_mv_setup_t dig_setup;
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extern ia64_mv_dma_alloc_coherent sba_alloc_coherent;
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extern ia64_mv_dma_free_coherent sba_free_coherent;
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extern ia64_mv_dma_map_single sba_map_single;
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@ -19,15 +18,15 @@ extern ia64_mv_dma_mapping_error sba_dma_mapping_error;
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* platform's machvec structure. When compiling a non-generic kernel,
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* the macros are used directly.
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*/
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#define platform_name "hpzx1"
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#define platform_setup sba_setup
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#define platform_dma_init machvec_noop
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#define platform_dma_alloc_coherent sba_alloc_coherent
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#define platform_dma_free_coherent sba_free_coherent
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#define platform_dma_map_single sba_map_single
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#define platform_dma_unmap_single sba_unmap_single
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#define platform_dma_map_sg sba_map_sg
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#define platform_dma_unmap_sg sba_unmap_sg
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#define platform_name "hpzx1"
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#define platform_setup dig_setup
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#define platform_dma_init machvec_noop
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#define platform_dma_alloc_coherent sba_alloc_coherent
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#define platform_dma_free_coherent sba_free_coherent
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#define platform_dma_map_single sba_map_single
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#define platform_dma_unmap_single sba_unmap_single
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#define platform_dma_map_sg sba_map_sg
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#define platform_dma_unmap_sg sba_unmap_sg
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#define platform_dma_sync_single_for_cpu machvec_dma_sync_single
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#define platform_dma_sync_sg_for_cpu machvec_dma_sync_sg
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#define platform_dma_sync_single_for_device machvec_dma_sync_single
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@ -2,7 +2,6 @@
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#define _ASM_IA64_MACHVEC_HPZX1_SWIOTLB_h
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extern ia64_mv_setup_t dig_setup;
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extern ia64_mv_dma_init hwsw_init;
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extern ia64_mv_dma_alloc_coherent hwsw_alloc_coherent;
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extern ia64_mv_dma_free_coherent hwsw_free_coherent;
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extern ia64_mv_dma_map_single hwsw_map_single;
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@ -26,7 +25,7 @@ extern ia64_mv_dma_sync_sg_for_device hwsw_sync_sg_for_device;
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#define platform_name "hpzx1_swiotlb"
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#define platform_setup dig_setup
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#define platform_dma_init hwsw_init
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#define platform_dma_init machvec_noop
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#define platform_dma_alloc_coherent hwsw_alloc_coherent
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#define platform_dma_free_coherent hwsw_free_coherent
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#define platform_dma_map_single hwsw_map_single
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