drm/i915: Dumb down the semaphore logic
While I think the previous code is correct, it was hard to follow and hard to debug. Since we already have a ring abstraction, might as well use it to handle the semaphore updates and compares. I don't expect this code to make semaphores better or worse, but you never know... v2: Remove magic per Keith's suggestions. Ran Daniel's gem_ring_sync_loop test on this. v3: Ignored one of Keith's suggestions. v4: Removed some bloat per Daniel's recommendation. Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Keith Packard <keithp@keithp.com> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Keith Packard <keithp@keithp.com>
This commit is contained in:
Ben Widawsky
Keith Packard
Родитель
e0dac65ed4
Коммит
c8c99b0f0d
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@ -784,7 +784,8 @@ i915_gem_execbuffer_sync_rings(struct drm_i915_gem_object *obj,
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}
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from->sync_seqno[idx] = seqno;
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return intel_ring_sync(to, from, seqno - 1);
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return to->sync_to(to, from, seqno - 1);
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}
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static int
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@ -194,6 +194,13 @@
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#define MI_SEMAPHORE_UPDATE (1<<21)
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#define MI_SEMAPHORE_COMPARE (1<<20)
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#define MI_SEMAPHORE_REGISTER (1<<18)
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#define MI_SEMAPHORE_SYNC_RV (2<<16)
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#define MI_SEMAPHORE_SYNC_RB (0<<16)
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#define MI_SEMAPHORE_SYNC_VR (0<<16)
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#define MI_SEMAPHORE_SYNC_VB (2<<16)
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#define MI_SEMAPHORE_SYNC_BR (2<<16)
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#define MI_SEMAPHORE_SYNC_BV (0<<16)
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#define MI_SEMAPHORE_SYNC_INVALID (1<<0)
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/*
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* 3D instructions used by the kernel
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*/
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@ -296,6 +303,12 @@
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#define RING_CTL(base) ((base)+0x3c)
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#define RING_SYNC_0(base) ((base)+0x40)
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#define RING_SYNC_1(base) ((base)+0x44)
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#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
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#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
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#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
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#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
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#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
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#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
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#define RING_MAX_IDLE(base) ((base)+0x54)
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#define RING_HWS_PGA(base) ((base)+0x80)
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#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
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@ -315,79 +315,127 @@ static void render_ring_cleanup(struct intel_ring_buffer *ring)
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}
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static void
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update_semaphore(struct intel_ring_buffer *ring, int i, u32 seqno)
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update_mboxes(struct intel_ring_buffer *ring,
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u32 seqno,
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u32 mmio_offset)
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{
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struct drm_device *dev = ring->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int id;
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/*
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* cs -> 1 = vcs, 0 = bcs
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* vcs -> 1 = bcs, 0 = cs,
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* bcs -> 1 = cs, 0 = vcs.
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*/
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id = ring - dev_priv->ring;
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id += 2 - i;
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id %= 3;
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intel_ring_emit(ring,
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MI_SEMAPHORE_MBOX |
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MI_SEMAPHORE_REGISTER |
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MI_SEMAPHORE_UPDATE);
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intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
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MI_SEMAPHORE_GLOBAL_GTT |
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MI_SEMAPHORE_REGISTER |
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MI_SEMAPHORE_UPDATE);
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intel_ring_emit(ring, seqno);
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intel_ring_emit(ring,
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RING_SYNC_0(dev_priv->ring[id].mmio_base) + 4*i);
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intel_ring_emit(ring, mmio_offset);
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}
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/**
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* gen6_add_request - Update the semaphore mailbox registers
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*
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* @ring - ring that is adding a request
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* @seqno - return seqno stuck into the ring
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*
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* Update the mailbox registers in the *other* rings with the current seqno.
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* This acts like a signal in the canonical semaphore.
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*/
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static int
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gen6_add_request(struct intel_ring_buffer *ring,
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u32 *result)
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u32 *seqno)
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{
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u32 seqno;
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u32 mbox1_reg;
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u32 mbox2_reg;
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int ret;
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ret = intel_ring_begin(ring, 10);
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if (ret)
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return ret;
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seqno = i915_gem_get_seqno(ring->dev);
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update_semaphore(ring, 0, seqno);
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update_semaphore(ring, 1, seqno);
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mbox1_reg = ring->signal_mbox[0];
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mbox2_reg = ring->signal_mbox[1];
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*seqno = i915_gem_get_seqno(ring->dev);
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update_mboxes(ring, *seqno, mbox1_reg);
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update_mboxes(ring, *seqno, mbox2_reg);
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intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
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intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
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intel_ring_emit(ring, seqno);
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intel_ring_emit(ring, *seqno);
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intel_ring_emit(ring, MI_USER_INTERRUPT);
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intel_ring_advance(ring);
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*result = seqno;
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return 0;
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}
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int
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intel_ring_sync(struct intel_ring_buffer *ring,
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struct intel_ring_buffer *to,
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/**
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* intel_ring_sync - sync the waiter to the signaller on seqno
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*
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* @waiter - ring that is waiting
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* @signaller - ring which has, or will signal
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* @seqno - seqno which the waiter will block on
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*/
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static int
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intel_ring_sync(struct intel_ring_buffer *waiter,
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struct intel_ring_buffer *signaller,
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int ring,
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u32 seqno)
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{
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int ret;
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u32 dw1 = MI_SEMAPHORE_MBOX |
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MI_SEMAPHORE_COMPARE |
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MI_SEMAPHORE_REGISTER;
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ret = intel_ring_begin(ring, 4);
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ret = intel_ring_begin(waiter, 4);
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if (ret)
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return ret;
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intel_ring_emit(ring,
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MI_SEMAPHORE_MBOX |
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MI_SEMAPHORE_REGISTER |
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intel_ring_sync_index(ring, to) << 17 |
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MI_SEMAPHORE_COMPARE);
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intel_ring_emit(ring, seqno);
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intel_ring_emit(ring, 0);
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intel_ring_emit(ring, MI_NOOP);
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intel_ring_advance(ring);
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intel_ring_emit(waiter, dw1 | signaller->semaphore_register[ring]);
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intel_ring_emit(waiter, seqno);
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intel_ring_emit(waiter, 0);
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intel_ring_emit(waiter, MI_NOOP);
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intel_ring_advance(waiter);
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return 0;
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}
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/* VCS->RCS (RVSYNC) or BCS->RCS (RBSYNC) */
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int
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render_ring_sync_to(struct intel_ring_buffer *waiter,
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struct intel_ring_buffer *signaller,
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u32 seqno)
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{
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WARN_ON(signaller->semaphore_register[RCS] == MI_SEMAPHORE_SYNC_INVALID);
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return intel_ring_sync(waiter,
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signaller,
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RCS,
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seqno);
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}
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/* RCS->VCS (VRSYNC) or BCS->VCS (VBSYNC) */
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int
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gen6_bsd_ring_sync_to(struct intel_ring_buffer *waiter,
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struct intel_ring_buffer *signaller,
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u32 seqno)
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{
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WARN_ON(signaller->semaphore_register[VCS] == MI_SEMAPHORE_SYNC_INVALID);
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return intel_ring_sync(waiter,
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signaller,
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VCS,
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seqno);
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}
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/* RCS->BCS (BRSYNC) or VCS->BCS (BVSYNC) */
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int
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gen6_blt_ring_sync_to(struct intel_ring_buffer *waiter,
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struct intel_ring_buffer *signaller,
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u32 seqno)
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{
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WARN_ON(signaller->semaphore_register[BCS] == MI_SEMAPHORE_SYNC_INVALID);
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return intel_ring_sync(waiter,
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signaller,
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BCS,
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seqno);
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}
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#define PIPE_CONTROL_FLUSH(ring__, addr__) \
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do { \
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intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \
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@ -1027,6 +1075,11 @@ static const struct intel_ring_buffer render_ring = {
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.irq_put = render_ring_put_irq,
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.dispatch_execbuffer = render_ring_dispatch_execbuffer,
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.cleanup = render_ring_cleanup,
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.sync_to = render_ring_sync_to,
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.semaphore_register = {MI_SEMAPHORE_SYNC_INVALID,
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MI_SEMAPHORE_SYNC_RV,
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MI_SEMAPHORE_SYNC_RB},
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.signal_mbox = {GEN6_VRSYNC, GEN6_BRSYNC},
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};
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/* ring buffer for bit-stream decoder */
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@ -1154,6 +1207,11 @@ static const struct intel_ring_buffer gen6_bsd_ring = {
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.irq_get = gen6_bsd_ring_get_irq,
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.irq_put = gen6_bsd_ring_put_irq,
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.dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
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.sync_to = gen6_bsd_ring_sync_to,
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.semaphore_register = {MI_SEMAPHORE_SYNC_VR,
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MI_SEMAPHORE_SYNC_INVALID,
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MI_SEMAPHORE_SYNC_VB},
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.signal_mbox = {GEN6_RVSYNC, GEN6_BVSYNC},
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};
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/* Blitter support (SandyBridge+) */
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@ -1281,10 +1339,15 @@ static const struct intel_ring_buffer gen6_blt_ring = {
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.flush = blt_ring_flush,
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.add_request = gen6_add_request,
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.get_seqno = ring_get_seqno,
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.irq_get = blt_ring_get_irq,
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.irq_put = blt_ring_put_irq,
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.irq_get = blt_ring_get_irq,
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.irq_put = blt_ring_put_irq,
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.dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
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.cleanup = blt_ring_cleanup,
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.cleanup = blt_ring_cleanup,
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.sync_to = gen6_blt_ring_sync_to,
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.semaphore_register = {MI_SEMAPHORE_SYNC_BR,
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MI_SEMAPHORE_SYNC_BV,
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MI_SEMAPHORE_SYNC_INVALID},
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.signal_mbox = {GEN6_RBSYNC, GEN6_VBSYNC},
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};
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int intel_init_render_ring_buffer(struct drm_device *dev)
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@ -75,7 +75,12 @@ struct intel_ring_buffer {
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int (*dispatch_execbuffer)(struct intel_ring_buffer *ring,
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u32 offset, u32 length);
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void (*cleanup)(struct intel_ring_buffer *ring);
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int (*sync_to)(struct intel_ring_buffer *ring,
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struct intel_ring_buffer *to,
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u32 seqno);
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u32 semaphore_register[3]; /*our mbox written by others */
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u32 signal_mbox[2]; /* mboxes this ring signals to */
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/**
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* List of objects currently involved in rendering from the
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* ringbuffer.
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@ -180,9 +185,6 @@ static inline void intel_ring_emit(struct intel_ring_buffer *ring,
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void intel_ring_advance(struct intel_ring_buffer *ring);
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u32 intel_ring_get_seqno(struct intel_ring_buffer *ring);
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int intel_ring_sync(struct intel_ring_buffer *ring,
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struct intel_ring_buffer *to,
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u32 seqno);
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int intel_init_render_ring_buffer(struct drm_device *dev);
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int intel_init_bsd_ring_buffer(struct drm_device *dev);
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