amd64_edac: Sanitize f10_get_base_addr_offset
This function maps the system address to the normalized DCT address. Document what the code does for more clarity and wrap insane bitmasks in a more understandable macro which generates them. Also, reduce number of arguments passed to the function. Finally, rename this function to what it actually does. No functional change. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
This commit is contained in:
Borislav Petkov
Родитель
229a7a11ac
Коммит
c8e518d567
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@ -460,13 +460,12 @@ int amd64_get_dram_hole_info(struct mem_ctl_info *mci, u64 *hole_base,
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}
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/* valid for Fam10h and above */
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if (boot_cpu_data.x86 >= 0x10 &&
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(pvt->dhar & DRAM_MEM_HOIST_VALID) == 0) {
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if (boot_cpu_data.x86 >= 0x10 && !dhar_mem_hoist_valid(pvt)) {
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debugf1(" Dram Memory Hoisting is DISABLED on this system\n");
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return 1;
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}
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if ((pvt->dhar & DHAR_VALID) == 0) {
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if (!dhar_valid(pvt)) {
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debugf1(" Dram Memory Hoisting is DISABLED on this node %d\n",
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pvt->mc_node_id);
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return 1;
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@ -859,8 +858,7 @@ static void dump_misc_regs(struct amd64_pvt *pvt)
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(boot_cpu_data.x86 == 0xf) ? k8_dhar_offset(pvt)
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: f10_dhar_offset(pvt));
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debugf1(" DramHoleValid: %s\n",
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(pvt->dhar & DHAR_VALID) ? "yes" : "no");
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debugf1(" DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
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amd64_debug_display_dimm_sizes(0, pvt);
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@ -1238,30 +1236,53 @@ static u8 f10_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
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return 0;
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}
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/* See F10h BKDG, 2.8.10.2 DctSelBaseOffset Programming */
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static inline u64 f10_get_base_addr_offset(u64 sys_addr, bool hi_range_sel,
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u32 dct_sel_base_addr,
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u64 dct_sel_base_off,
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u32 hole_valid, u64 hole_off,
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u64 dram_base)
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/* Convert the sys_addr to the normalized DCT address */
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static u64 f10_get_norm_dct_addr(struct amd64_pvt *pvt, int range,
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u64 sys_addr, bool hi_rng,
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u32 dct_sel_base_addr)
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{
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u64 chan_off;
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u64 dram_base = get_dram_base(pvt, range);
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u64 hole_off = f10_dhar_offset(pvt);
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u32 hole_valid = dhar_valid(pvt);
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u64 dct_sel_base_off = (pvt->dct_sel_hi & 0xFFFFFC00) << 16;
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if (hi_range_sel) {
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if (!(dct_sel_base_addr & 0xFFFF0000) &&
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hole_valid && (sys_addr >= 0x100000000ULL))
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if (hi_rng) {
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/*
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* if
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* base address of high range is below 4Gb
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* (bits [47:27] at [31:11])
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* DRAM address space on this DCT is hoisted above 4Gb &&
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* sys_addr > 4Gb
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*
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* remove hole offset from sys_addr
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* else
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* remove high range offset from sys_addr
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*/
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if ((!(dct_sel_base_addr >> 16) ||
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dct_sel_base_addr < dhar_base(pvt)) &&
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hole_valid &&
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(sys_addr >= BIT_64(32)))
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chan_off = hole_off;
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else
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chan_off = dct_sel_base_off;
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} else {
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if (hole_valid && (sys_addr >= 0x100000000ULL))
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/*
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* if
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* we have a valid hole &&
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* sys_addr > 4Gb
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*
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* remove hole
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* else
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* remove dram base to normalize to DCT address
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*/
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if (hole_valid && (sys_addr >= BIT_64(32)))
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chan_off = hole_off;
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else
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chan_off = dram_base & 0xFFFFF8000000ULL;
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chan_off = dram_base;
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}
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return (sys_addr & 0x0000FFFFFFFFFFC0ULL) -
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(chan_off & 0x0000FFFFFF800000ULL);
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return (sys_addr & GENMASK(6,47)) - (chan_off & GENMASK(23,47));
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}
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/* Hack for the time being - Can we get this from BIOS?? */
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@ -1346,30 +1367,17 @@ static int f10_match_to_this_node(struct amd64_pvt *pvt, int range,
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u64 sys_addr, int *nid, int *chan_sel)
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{
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int cs_found = -EINVAL;
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u64 chan_addr, dct_sel_base_off;
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u64 hole_off;
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u32 hole_valid, tmp, dct_sel_base;
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u64 chan_addr;
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u32 tmp, dct_sel_base;
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u8 channel;
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bool high_range = false;
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u8 node_id = dram_dst_node(pvt, range);
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u8 intlv_en = dram_intlv_en(pvt, range);
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u32 intlv_sel = dram_intlv_sel(pvt, range);
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u64 dram_base = get_dram_base(pvt, range);
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debugf1("(range %d) Base=0x%llx SystemAddr= 0x%llx Limit=0x%llx\n",
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range, dram_base, sys_addr, get_dram_limit(pvt, range));
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/*
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* This assumes that one node's DHAR is the same as all the other
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* nodes' DHAR.
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*/
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hole_off = f10_dhar_offset(pvt);
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hole_valid = (pvt->dhar & DHAR_VALID);
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dct_sel_base_off = (pvt->dct_sel_hi & 0xFFFFFC00) << 16;
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debugf1(" HoleOffset=0x%016llx HoleValid=%d IntlvSel=0x%x\n",
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hole_off, hole_valid, intlv_sel);
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debugf1("(range %d) SystemAddr= 0x%llx Limit=0x%llx\n",
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range, sys_addr, get_dram_limit(pvt, range));
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if (intlv_en &&
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(intlv_sel != ((sys_addr >> 12) & intlv_en)))
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@ -1388,9 +1396,8 @@ static int f10_match_to_this_node(struct amd64_pvt *pvt, int range,
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channel = f10_determine_channel(pvt, sys_addr, high_range, intlv_en);
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chan_addr = f10_get_base_addr_offset(sys_addr, high_range, dct_sel_base,
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dct_sel_base_off, hole_valid,
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hole_off, dram_base);
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chan_addr = f10_get_norm_dct_addr(pvt, range, sys_addr,
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high_range, dct_sel_base);
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/* remove Node ID (in case of memory interleaving) */
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tmp = chan_addr & 0xFC0;
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@ -184,18 +184,13 @@
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#define dram_dst_node(pvt, i) (pvt->ranges[i].lim.lo & 0x7)
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#define DHAR 0xf0
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#define DHAR_VALID BIT(0)
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#define DRAM_MEM_HOIST_VALID BIT(1)
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#define dhar_valid(pvt) ((pvt)->dhar & BIT(0))
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#define dhar_mem_hoist_valid(pvt) ((pvt)->dhar & BIT(1))
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#define dhar_base(pvt) ((pvt)->dhar & 0xff000000)
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#define k8_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff00) << 16)
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#define DHAR_BASE_MASK 0xff000000
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#define dhar_base(pvt) ((pvt)->dhar & DHAR_BASE_MASK)
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#define K8_DHAR_OFFSET_MASK 0x0000ff00
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#define k8_dhar_offset(pvt) (((pvt)->dhar & K8_DHAR_OFFSET_MASK) << 16)
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#define F10_DHAR_OFFSET_MASK 0x0000ff80
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/* NOTE: Extra mask bit vs K8 */
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#define f10_dhar_offset(pvt) (((pvt)->dhar & F10_DHAR_OFFSET_MASK) << 16)
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#define f10_dhar_offset(pvt) (((pvt)->dhar & 0x0000ff80) << 16)
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#define DCT_CFG_SEL 0x10C
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