Disintegrate asm/system.h for M32R
Disintegrate asm/system.h for M32R. Signed-off-by: David Howells <dhowells@redhat.com> cc: linux-m32r@ml.linux-m32r.org
This commit is contained in:
David Howells
Родитель
c140d87995
Коммит
c9034c3a1d
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@ -11,7 +11,8 @@
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#include <linux/types.h>
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#include <asm/assembler.h>
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#include <asm/system.h>
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#include <asm/cmpxchg.h>
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#include <asm/dcache_clear.h>
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/*
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* Atomic operations that C can't guarantee us. Useful for
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@ -0,0 +1,94 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto
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* Copyright (C) 2004, 2006 Hirokazu Takata <takata at linux-m32r.org>
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*/
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#ifndef _ASM_M32R_BARRIER_H
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#define _ASM_M32R_BARRIER_H
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#define nop() __asm__ __volatile__ ("nop" : : )
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/*
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* Memory barrier.
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*
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* mb() prevents loads and stores being reordered across this point.
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* rmb() prevents loads being reordered across this point.
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* wmb() prevents stores being reordered across this point.
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*/
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#define mb() barrier()
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#define rmb() mb()
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#define wmb() mb()
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/**
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* read_barrier_depends - Flush all pending reads that subsequents reads
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* depend on.
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*
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* No data-dependent reads from memory-like regions are ever reordered
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* over this barrier. All reads preceding this primitive are guaranteed
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* to access memory (but not necessarily other CPUs' caches) before any
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* reads following this primitive that depend on the data return by
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* any of the preceding reads. This primitive is much lighter weight than
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* rmb() on most CPUs, and is never heavier weight than is
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* rmb().
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*
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* These ordering constraints are respected by both the local CPU
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* and the compiler.
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*
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* Ordering is not guaranteed by anything other than these primitives,
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* not even by data dependencies. See the documentation for
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* memory_barrier() for examples and URLs to more information.
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*
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* For example, the following code would force ordering (the initial
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* value of "a" is zero, "b" is one, and "p" is "&a"):
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*
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* <programlisting>
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* CPU 0 CPU 1
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*
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* b = 2;
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* memory_barrier();
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* p = &b; q = p;
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* read_barrier_depends();
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* d = *q;
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* </programlisting>
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*
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*
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* because the read of "*q" depends on the read of "p" and these
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* two reads are separated by a read_barrier_depends(). However,
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* the following code, with the same initial values for "a" and "b":
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*
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* <programlisting>
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* CPU 0 CPU 1
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*
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* a = 2;
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* memory_barrier();
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* b = 3; y = b;
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* read_barrier_depends();
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* x = a;
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* </programlisting>
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*
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* does not enforce ordering, since there is no data dependency between
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* the read of "a" and the read of "b". Therefore, on some CPUs, such
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* as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
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* in cases like this where there are no data dependencies.
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**/
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#define read_barrier_depends() do { } while (0)
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#ifdef CONFIG_SMP
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#define smp_mb() mb()
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#define smp_rmb() rmb()
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#define smp_wmb() wmb()
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#define smp_read_barrier_depends() read_barrier_depends()
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#define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
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#else
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#define smp_mb() barrier()
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#define smp_rmb() barrier()
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#define smp_wmb() barrier()
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#define smp_read_barrier_depends() do { } while (0)
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#define set_mb(var, value) do { var = value; barrier(); } while (0)
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#endif
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#endif /* _ASM_M32R_BARRIER_H */
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@ -16,9 +16,10 @@
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#endif
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#include <linux/compiler.h>
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#include <linux/irqflags.h>
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#include <asm/assembler.h>
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#include <asm/system.h>
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#include <asm/byteorder.h>
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#include <asm/dcache_clear.h>
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#include <asm/types.h>
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/*
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@ -0,0 +1,221 @@
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#ifndef _ASM_M32R_CMPXCHG_H
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#define _ASM_M32R_CMPXCHG_H
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/*
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* M32R version:
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* Copyright (C) 2001, 2002 Hitoshi Yamamoto
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* Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
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*/
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#include <linux/irqflags.h>
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#include <asm/assembler.h>
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#include <asm/dcache_clear.h>
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extern void __xchg_called_with_bad_pointer(void);
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static __always_inline unsigned long
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__xchg(unsigned long x, volatile void *ptr, int size)
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{
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unsigned long flags;
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unsigned long tmp = 0;
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local_irq_save(flags);
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switch (size) {
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#ifndef CONFIG_SMP
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case 1:
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__asm__ __volatile__ (
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"ldb %0, @%2 \n\t"
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"stb %1, @%2 \n\t"
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: "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
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break;
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case 2:
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__asm__ __volatile__ (
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"ldh %0, @%2 \n\t"
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"sth %1, @%2 \n\t"
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: "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
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break;
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case 4:
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__asm__ __volatile__ (
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"ld %0, @%2 \n\t"
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"st %1, @%2 \n\t"
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: "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
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break;
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#else /* CONFIG_SMP */
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case 4:
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__asm__ __volatile__ (
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DCACHE_CLEAR("%0", "r4", "%2")
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"lock %0, @%2; \n\t"
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"unlock %1, @%2; \n\t"
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: "=&r" (tmp) : "r" (x), "r" (ptr)
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: "memory"
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#ifdef CONFIG_CHIP_M32700_TS1
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, "r4"
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#endif /* CONFIG_CHIP_M32700_TS1 */
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);
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break;
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#endif /* CONFIG_SMP */
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default:
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__xchg_called_with_bad_pointer();
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}
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local_irq_restore(flags);
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return (tmp);
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}
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#define xchg(ptr, x) \
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((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr))))
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static __always_inline unsigned long
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__xchg_local(unsigned long x, volatile void *ptr, int size)
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{
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unsigned long flags;
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unsigned long tmp = 0;
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local_irq_save(flags);
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switch (size) {
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case 1:
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__asm__ __volatile__ (
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"ldb %0, @%2 \n\t"
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"stb %1, @%2 \n\t"
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: "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
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break;
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case 2:
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__asm__ __volatile__ (
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"ldh %0, @%2 \n\t"
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"sth %1, @%2 \n\t"
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: "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
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break;
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case 4:
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__asm__ __volatile__ (
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"ld %0, @%2 \n\t"
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"st %1, @%2 \n\t"
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: "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
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break;
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default:
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__xchg_called_with_bad_pointer();
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}
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local_irq_restore(flags);
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return (tmp);
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}
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#define xchg_local(ptr, x) \
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((__typeof__(*(ptr)))__xchg_local((unsigned long)(x), (ptr), \
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sizeof(*(ptr))))
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#define __HAVE_ARCH_CMPXCHG 1
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static inline unsigned long
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__cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new)
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{
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unsigned long flags;
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unsigned int retval;
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local_irq_save(flags);
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__asm__ __volatile__ (
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DCACHE_CLEAR("%0", "r4", "%1")
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M32R_LOCK" %0, @%1; \n"
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" bne %0, %2, 1f; \n"
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M32R_UNLOCK" %3, @%1; \n"
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" bra 2f; \n"
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" .fillinsn \n"
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"1:"
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M32R_UNLOCK" %0, @%1; \n"
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" .fillinsn \n"
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"2:"
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: "=&r" (retval)
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: "r" (p), "r" (old), "r" (new)
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: "cbit", "memory"
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#ifdef CONFIG_CHIP_M32700_TS1
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, "r4"
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#endif /* CONFIG_CHIP_M32700_TS1 */
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);
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local_irq_restore(flags);
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return retval;
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}
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static inline unsigned long
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__cmpxchg_local_u32(volatile unsigned int *p, unsigned int old,
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unsigned int new)
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{
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unsigned long flags;
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unsigned int retval;
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local_irq_save(flags);
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__asm__ __volatile__ (
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DCACHE_CLEAR("%0", "r4", "%1")
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"ld %0, @%1; \n"
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" bne %0, %2, 1f; \n"
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"st %3, @%1; \n"
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" bra 2f; \n"
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" .fillinsn \n"
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"1:"
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"st %0, @%1; \n"
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" .fillinsn \n"
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"2:"
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: "=&r" (retval)
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: "r" (p), "r" (old), "r" (new)
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: "cbit", "memory"
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#ifdef CONFIG_CHIP_M32700_TS1
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, "r4"
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#endif /* CONFIG_CHIP_M32700_TS1 */
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);
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local_irq_restore(flags);
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return retval;
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}
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/* This function doesn't exist, so you'll get a linker error
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if something tries to do an invalid cmpxchg(). */
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extern void __cmpxchg_called_with_bad_pointer(void);
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static inline unsigned long
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__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
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{
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switch (size) {
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case 4:
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return __cmpxchg_u32(ptr, old, new);
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#if 0 /* we don't have __cmpxchg_u64 */
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case 8:
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return __cmpxchg_u64(ptr, old, new);
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#endif /* 0 */
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}
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__cmpxchg_called_with_bad_pointer();
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return old;
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}
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#define cmpxchg(ptr, o, n) \
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((__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)(o), \
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(unsigned long)(n), sizeof(*(ptr))))
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#include <asm-generic/cmpxchg-local.h>
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static inline unsigned long __cmpxchg_local(volatile void *ptr,
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unsigned long old,
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unsigned long new, int size)
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{
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switch (size) {
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case 4:
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return __cmpxchg_local_u32(ptr, old, new);
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default:
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return __cmpxchg_local_generic(ptr, old, new, size);
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}
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return old;
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}
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/*
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* cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
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* them available.
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*/
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#define cmpxchg_local(ptr, o, n) \
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((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
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(unsigned long)(n), sizeof(*(ptr))))
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#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
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#endif /* _ASM_M32R_CMPXCHG_H */
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@ -0,0 +1,29 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
|
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* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
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* Copyright (C) 2001 Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto
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* Copyright (C) 2004, 2006 Hirokazu Takata <takata at linux-m32r.org>
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*/
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#ifndef _ASM_M32R_DCACHE_CLEAR_H
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#define _ASM_M32R_DCACHE_CLEAR_H
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#ifdef CONFIG_CHIP_M32700_TS1
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#define DCACHE_CLEAR(reg0, reg1, addr) \
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"seth "reg1", #high(dcache_dummy); \n\t" \
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"or3 "reg1", "reg1", #low(dcache_dummy); \n\t" \
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"lock "reg0", @"reg1"; \n\t" \
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"add3 "reg0", "addr", #0x1000; \n\t" \
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"ld "reg0", @"reg0"; \n\t" \
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"add3 "reg0", "addr", #0x2000; \n\t" \
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"ld "reg0", @"reg0"; \n\t" \
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"unlock "reg0", @"reg1"; \n\t"
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/* FIXME: This workaround code cannot handle kernel modules
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* correctly under SMP environment.
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*/
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#else /* CONFIG_CHIP_M32700_TS1 */
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#define DCACHE_CLEAR(reg0, reg1, addr)
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#endif /* CONFIG_CHIP_M32700_TS1 */
|
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#endif /* _ASM_M32R_DCACHE_CLEAR_H */
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|
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@ -0,0 +1,14 @@
|
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/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2001 Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto
|
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* Copyright (C) 2004, 2006 Hirokazu Takata <takata at linux-m32r.org>
|
||||
*/
|
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#ifndef _ASM_M32R_EXEC_H
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#define _ASM_M32R_EXEC_H
|
||||
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#define arch_align_stack(x) (x)
|
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#endif /* _ASM_M32R_EXEC_H */
|
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|
|
@ -12,7 +12,6 @@
|
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|
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#include <linux/percpu.h>
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#include <asm/assembler.h>
|
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#include <asm/system.h>
|
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#include <asm/local.h>
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -11,6 +11,7 @@
|
|||
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/atomic.h>
|
||||
#include <asm/dcache_clear.h>
|
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#include <asm/page.h>
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -0,0 +1,51 @@
|
|||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2001 Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto
|
||||
* Copyright (C) 2004, 2006 Hirokazu Takata <takata at linux-m32r.org>
|
||||
*/
|
||||
#ifndef _ASM_M32R_SWITCH_TO_H
|
||||
#define _ASM_M32R_SWITCH_TO_H
|
||||
|
||||
/*
|
||||
* switch_to(prev, next) should switch from task `prev' to `next'
|
||||
* `prev' will never be the same as `next'.
|
||||
*
|
||||
* `next' and `prev' should be struct task_struct, but it isn't always defined
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_FRAME_POINTER) || \
|
||||
!defined(CONFIG_SCHED_OMIT_FRAME_POINTER)
|
||||
#define M32R_PUSH_FP " push fp\n"
|
||||
#define M32R_POP_FP " pop fp\n"
|
||||
#else
|
||||
#define M32R_PUSH_FP ""
|
||||
#define M32R_POP_FP ""
|
||||
#endif
|
||||
|
||||
#define switch_to(prev, next, last) do { \
|
||||
__asm__ __volatile__ ( \
|
||||
" seth lr, #high(1f) \n" \
|
||||
" or3 lr, lr, #low(1f) \n" \
|
||||
" st lr, @%4 ; store old LR \n" \
|
||||
" ld lr, @%5 ; load new LR \n" \
|
||||
M32R_PUSH_FP \
|
||||
" st sp, @%2 ; store old SP \n" \
|
||||
" ld sp, @%3 ; load new SP \n" \
|
||||
" push %1 ; store `prev' on new stack \n" \
|
||||
" jmp lr \n" \
|
||||
" .fillinsn \n" \
|
||||
"1: \n" \
|
||||
" pop %0 ; restore `__last' from new stack \n" \
|
||||
M32R_POP_FP \
|
||||
: "=r" (last) \
|
||||
: "0" (prev), \
|
||||
"r" (&(prev->thread.sp)), "r" (&(next->thread.sp)), \
|
||||
"r" (&(prev->thread.lr)), "r" (&(next->thread.lr)) \
|
||||
: "memory", "lr" \
|
||||
); \
|
||||
} while(0)
|
||||
|
||||
#endif /* _ASM_M32R_SWITCH_TO_H */
|
||||
|
|
@ -1,367 +1,6 @@
|
|||
#ifndef _ASM_M32R_SYSTEM_H
|
||||
#define _ASM_M32R_SYSTEM_H
|
||||
|
||||
/*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*
|
||||
* Copyright (C) 2001 Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto
|
||||
* Copyright (C) 2004, 2006 Hirokazu Takata <takata at linux-m32r.org>
|
||||
*/
|
||||
|
||||
#include <linux/compiler.h>
|
||||
#include <linux/irqflags.h>
|
||||
#include <asm/assembler.h>
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
/*
|
||||
* switch_to(prev, next) should switch from task `prev' to `next'
|
||||
* `prev' will never be the same as `next'.
|
||||
*
|
||||
* `next' and `prev' should be struct task_struct, but it isn't always defined
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_FRAME_POINTER) || \
|
||||
!defined(CONFIG_SCHED_OMIT_FRAME_POINTER)
|
||||
#define M32R_PUSH_FP " push fp\n"
|
||||
#define M32R_POP_FP " pop fp\n"
|
||||
#else
|
||||
#define M32R_PUSH_FP ""
|
||||
#define M32R_POP_FP ""
|
||||
#endif
|
||||
|
||||
#define switch_to(prev, next, last) do { \
|
||||
__asm__ __volatile__ ( \
|
||||
" seth lr, #high(1f) \n" \
|
||||
" or3 lr, lr, #low(1f) \n" \
|
||||
" st lr, @%4 ; store old LR \n" \
|
||||
" ld lr, @%5 ; load new LR \n" \
|
||||
M32R_PUSH_FP \
|
||||
" st sp, @%2 ; store old SP \n" \
|
||||
" ld sp, @%3 ; load new SP \n" \
|
||||
" push %1 ; store `prev' on new stack \n" \
|
||||
" jmp lr \n" \
|
||||
" .fillinsn \n" \
|
||||
"1: \n" \
|
||||
" pop %0 ; restore `__last' from new stack \n" \
|
||||
M32R_POP_FP \
|
||||
: "=r" (last) \
|
||||
: "0" (prev), \
|
||||
"r" (&(prev->thread.sp)), "r" (&(next->thread.sp)), \
|
||||
"r" (&(prev->thread.lr)), "r" (&(next->thread.lr)) \
|
||||
: "memory", "lr" \
|
||||
); \
|
||||
} while(0)
|
||||
|
||||
#define nop() __asm__ __volatile__ ("nop" : : )
|
||||
|
||||
#define xchg(ptr, x) \
|
||||
((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr))))
|
||||
#define xchg_local(ptr, x) \
|
||||
((__typeof__(*(ptr)))__xchg_local((unsigned long)(x), (ptr), \
|
||||
sizeof(*(ptr))))
|
||||
|
||||
extern void __xchg_called_with_bad_pointer(void);
|
||||
|
||||
#ifdef CONFIG_CHIP_M32700_TS1
|
||||
#define DCACHE_CLEAR(reg0, reg1, addr) \
|
||||
"seth "reg1", #high(dcache_dummy); \n\t" \
|
||||
"or3 "reg1", "reg1", #low(dcache_dummy); \n\t" \
|
||||
"lock "reg0", @"reg1"; \n\t" \
|
||||
"add3 "reg0", "addr", #0x1000; \n\t" \
|
||||
"ld "reg0", @"reg0"; \n\t" \
|
||||
"add3 "reg0", "addr", #0x2000; \n\t" \
|
||||
"ld "reg0", @"reg0"; \n\t" \
|
||||
"unlock "reg0", @"reg1"; \n\t"
|
||||
/* FIXME: This workaround code cannot handle kernel modules
|
||||
* correctly under SMP environment.
|
||||
*/
|
||||
#else /* CONFIG_CHIP_M32700_TS1 */
|
||||
#define DCACHE_CLEAR(reg0, reg1, addr)
|
||||
#endif /* CONFIG_CHIP_M32700_TS1 */
|
||||
|
||||
static __always_inline unsigned long
|
||||
__xchg(unsigned long x, volatile void *ptr, int size)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned long tmp = 0;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
switch (size) {
|
||||
#ifndef CONFIG_SMP
|
||||
case 1:
|
||||
__asm__ __volatile__ (
|
||||
"ldb %0, @%2 \n\t"
|
||||
"stb %1, @%2 \n\t"
|
||||
: "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
|
||||
break;
|
||||
case 2:
|
||||
__asm__ __volatile__ (
|
||||
"ldh %0, @%2 \n\t"
|
||||
"sth %1, @%2 \n\t"
|
||||
: "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
|
||||
break;
|
||||
case 4:
|
||||
__asm__ __volatile__ (
|
||||
"ld %0, @%2 \n\t"
|
||||
"st %1, @%2 \n\t"
|
||||
: "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
|
||||
break;
|
||||
#else /* CONFIG_SMP */
|
||||
case 4:
|
||||
__asm__ __volatile__ (
|
||||
DCACHE_CLEAR("%0", "r4", "%2")
|
||||
"lock %0, @%2; \n\t"
|
||||
"unlock %1, @%2; \n\t"
|
||||
: "=&r" (tmp) : "r" (x), "r" (ptr)
|
||||
: "memory"
|
||||
#ifdef CONFIG_CHIP_M32700_TS1
|
||||
, "r4"
|
||||
#endif /* CONFIG_CHIP_M32700_TS1 */
|
||||
);
|
||||
break;
|
||||
#endif /* CONFIG_SMP */
|
||||
default:
|
||||
__xchg_called_with_bad_pointer();
|
||||
}
|
||||
|
||||
local_irq_restore(flags);
|
||||
|
||||
return (tmp);
|
||||
}
|
||||
|
||||
static __always_inline unsigned long
|
||||
__xchg_local(unsigned long x, volatile void *ptr, int size)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned long tmp = 0;
|
||||
|
||||
local_irq_save(flags);
|
||||
|
||||
switch (size) {
|
||||
case 1:
|
||||
__asm__ __volatile__ (
|
||||
"ldb %0, @%2 \n\t"
|
||||
"stb %1, @%2 \n\t"
|
||||
: "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
|
||||
break;
|
||||
case 2:
|
||||
__asm__ __volatile__ (
|
||||
"ldh %0, @%2 \n\t"
|
||||
"sth %1, @%2 \n\t"
|
||||
: "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
|
||||
break;
|
||||
case 4:
|
||||
__asm__ __volatile__ (
|
||||
"ld %0, @%2 \n\t"
|
||||
"st %1, @%2 \n\t"
|
||||
: "=&r" (tmp) : "r" (x), "r" (ptr) : "memory");
|
||||
break;
|
||||
default:
|
||||
__xchg_called_with_bad_pointer();
|
||||
}
|
||||
|
||||
local_irq_restore(flags);
|
||||
|
||||
return (tmp);
|
||||
}
|
||||
|
||||
#define __HAVE_ARCH_CMPXCHG 1
|
||||
|
||||
static inline unsigned long
|
||||
__cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned int retval;
|
||||
|
||||
local_irq_save(flags);
|
||||
__asm__ __volatile__ (
|
||||
DCACHE_CLEAR("%0", "r4", "%1")
|
||||
M32R_LOCK" %0, @%1; \n"
|
||||
" bne %0, %2, 1f; \n"
|
||||
M32R_UNLOCK" %3, @%1; \n"
|
||||
" bra 2f; \n"
|
||||
" .fillinsn \n"
|
||||
"1:"
|
||||
M32R_UNLOCK" %0, @%1; \n"
|
||||
" .fillinsn \n"
|
||||
"2:"
|
||||
: "=&r" (retval)
|
||||
: "r" (p), "r" (old), "r" (new)
|
||||
: "cbit", "memory"
|
||||
#ifdef CONFIG_CHIP_M32700_TS1
|
||||
, "r4"
|
||||
#endif /* CONFIG_CHIP_M32700_TS1 */
|
||||
);
|
||||
local_irq_restore(flags);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
static inline unsigned long
|
||||
__cmpxchg_local_u32(volatile unsigned int *p, unsigned int old,
|
||||
unsigned int new)
|
||||
{
|
||||
unsigned long flags;
|
||||
unsigned int retval;
|
||||
|
||||
local_irq_save(flags);
|
||||
__asm__ __volatile__ (
|
||||
DCACHE_CLEAR("%0", "r4", "%1")
|
||||
"ld %0, @%1; \n"
|
||||
" bne %0, %2, 1f; \n"
|
||||
"st %3, @%1; \n"
|
||||
" bra 2f; \n"
|
||||
" .fillinsn \n"
|
||||
"1:"
|
||||
"st %0, @%1; \n"
|
||||
" .fillinsn \n"
|
||||
"2:"
|
||||
: "=&r" (retval)
|
||||
: "r" (p), "r" (old), "r" (new)
|
||||
: "cbit", "memory"
|
||||
#ifdef CONFIG_CHIP_M32700_TS1
|
||||
, "r4"
|
||||
#endif /* CONFIG_CHIP_M32700_TS1 */
|
||||
);
|
||||
local_irq_restore(flags);
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/* This function doesn't exist, so you'll get a linker error
|
||||
if something tries to do an invalid cmpxchg(). */
|
||||
extern void __cmpxchg_called_with_bad_pointer(void);
|
||||
|
||||
static inline unsigned long
|
||||
__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
|
||||
{
|
||||
switch (size) {
|
||||
case 4:
|
||||
return __cmpxchg_u32(ptr, old, new);
|
||||
#if 0 /* we don't have __cmpxchg_u64 */
|
||||
case 8:
|
||||
return __cmpxchg_u64(ptr, old, new);
|
||||
#endif /* 0 */
|
||||
}
|
||||
__cmpxchg_called_with_bad_pointer();
|
||||
return old;
|
||||
}
|
||||
|
||||
#define cmpxchg(ptr, o, n) \
|
||||
((__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)(o), \
|
||||
(unsigned long)(n), sizeof(*(ptr))))
|
||||
|
||||
#include <asm-generic/cmpxchg-local.h>
|
||||
|
||||
static inline unsigned long __cmpxchg_local(volatile void *ptr,
|
||||
unsigned long old,
|
||||
unsigned long new, int size)
|
||||
{
|
||||
switch (size) {
|
||||
case 4:
|
||||
return __cmpxchg_local_u32(ptr, old, new);
|
||||
default:
|
||||
return __cmpxchg_local_generic(ptr, old, new, size);
|
||||
}
|
||||
|
||||
return old;
|
||||
}
|
||||
|
||||
/*
|
||||
* cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
|
||||
* them available.
|
||||
*/
|
||||
#define cmpxchg_local(ptr, o, n) \
|
||||
((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
|
||||
(unsigned long)(n), sizeof(*(ptr))))
|
||||
#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
/*
|
||||
* Memory barrier.
|
||||
*
|
||||
* mb() prevents loads and stores being reordered across this point.
|
||||
* rmb() prevents loads being reordered across this point.
|
||||
* wmb() prevents stores being reordered across this point.
|
||||
*/
|
||||
#define mb() barrier()
|
||||
#define rmb() mb()
|
||||
#define wmb() mb()
|
||||
|
||||
/**
|
||||
* read_barrier_depends - Flush all pending reads that subsequents reads
|
||||
* depend on.
|
||||
*
|
||||
* No data-dependent reads from memory-like regions are ever reordered
|
||||
* over this barrier. All reads preceding this primitive are guaranteed
|
||||
* to access memory (but not necessarily other CPUs' caches) before any
|
||||
* reads following this primitive that depend on the data return by
|
||||
* any of the preceding reads. This primitive is much lighter weight than
|
||||
* rmb() on most CPUs, and is never heavier weight than is
|
||||
* rmb().
|
||||
*
|
||||
* These ordering constraints are respected by both the local CPU
|
||||
* and the compiler.
|
||||
*
|
||||
* Ordering is not guaranteed by anything other than these primitives,
|
||||
* not even by data dependencies. See the documentation for
|
||||
* memory_barrier() for examples and URLs to more information.
|
||||
*
|
||||
* For example, the following code would force ordering (the initial
|
||||
* value of "a" is zero, "b" is one, and "p" is "&a"):
|
||||
*
|
||||
* <programlisting>
|
||||
* CPU 0 CPU 1
|
||||
*
|
||||
* b = 2;
|
||||
* memory_barrier();
|
||||
* p = &b; q = p;
|
||||
* read_barrier_depends();
|
||||
* d = *q;
|
||||
* </programlisting>
|
||||
*
|
||||
*
|
||||
* because the read of "*q" depends on the read of "p" and these
|
||||
* two reads are separated by a read_barrier_depends(). However,
|
||||
* the following code, with the same initial values for "a" and "b":
|
||||
*
|
||||
* <programlisting>
|
||||
* CPU 0 CPU 1
|
||||
*
|
||||
* a = 2;
|
||||
* memory_barrier();
|
||||
* b = 3; y = b;
|
||||
* read_barrier_depends();
|
||||
* x = a;
|
||||
* </programlisting>
|
||||
*
|
||||
* does not enforce ordering, since there is no data dependency between
|
||||
* the read of "a" and the read of "b". Therefore, on some CPUs, such
|
||||
* as Alpha, "y" could be set to 3 and "x" to 0. Use rmb()
|
||||
* in cases like this where there are no data dependencies.
|
||||
**/
|
||||
|
||||
#define read_barrier_depends() do { } while (0)
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
#define smp_mb() mb()
|
||||
#define smp_rmb() rmb()
|
||||
#define smp_wmb() wmb()
|
||||
#define smp_read_barrier_depends() read_barrier_depends()
|
||||
#define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
|
||||
#else
|
||||
#define smp_mb() barrier()
|
||||
#define smp_rmb() barrier()
|
||||
#define smp_wmb() barrier()
|
||||
#define smp_read_barrier_depends() do { } while (0)
|
||||
#define set_mb(var, value) do { var = value; barrier(); } while (0)
|
||||
#endif
|
||||
|
||||
#define arch_align_stack(x) (x)
|
||||
|
||||
#endif /* _ASM_M32R_SYSTEM_H */
|
||||
/* FILE TO BE DELETED. DO NOT ADD STUFF HERE! */
|
||||
#include <asm/barrier.h>
|
||||
#include <asm/cmpxchg.h>
|
||||
#include <asm/dcache_clear.h>
|
||||
#include <asm/exec.h>
|
||||
#include <asm/switch_to.h>
|
||||
|
|
|
|||
|
|
@ -29,7 +29,6 @@
|
|||
#include <asm/io.h>
|
||||
#include <asm/uaccess.h>
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/mmu_context.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -18,7 +18,6 @@
|
|||
#include <asm/page.h>
|
||||
#include <asm/processor.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/uaccess.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/atomic.h>
|
||||
|
|
|
|||
|
|
@ -22,7 +22,6 @@
|
|||
#include <linux/vt_kern.h> /* For unblank_screen() */
|
||||
|
||||
#include <asm/m32r.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/uaccess.h>
|
||||
#include <asm/pgalloc.h>
|
||||
#include <asm/pgtable.h>
|
||||
|
|
|
|||
|
|
@ -26,7 +26,6 @@
|
|||
#include <linux/module.h>
|
||||
|
||||
#include <asm/m32r.h>
|
||||
#include <asm/system.h>
|
||||
#include <asm/uaccess.h>
|
||||
#include <asm/hardirq.h>
|
||||
#include <asm/mmu_context.h>
|
||||
|
|
|
|||
|
|
@ -13,7 +13,6 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/device.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/m32r.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -16,7 +16,6 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/m32r.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -12,7 +12,6 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/m32r.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -12,7 +12,6 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/m32r.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -12,7 +12,6 @@
|
|||
#include <linux/init.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/m32r.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -11,7 +11,6 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
|
||||
#include <asm/system.h>
|
||||
#include <asm/m32r.h>
|
||||
#include <asm/io.h>
|
||||
|
||||
|
|
|
|||
|
|
@ -17,7 +17,6 @@
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <asm/system.h>
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#include <asm/m32r.h>
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#include <asm/io.h>
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@ -11,7 +11,6 @@
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <asm/system.h>
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#include <asm/m32r.h>
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#include <asm/io.h>
|
||||
|
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|
|
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Ссылка в новой задаче