Merge branch 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 platform updates from Ingo Molnar: "Misc platform updates: SGI UV4 support additions, intel-mid Merrifield enhancements and purge of old code" * 'x86-platform-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (21 commits) x86/platform/UV/NMI: Fix uneccessary kABI breakage x86/platform/UV: Clean up the NMI code to match current coding style x86/platform/UV: Ensure uv_system_init is called when necessary x86/platform/UV: Initialize PCH GPP_D_0 NMI Pin to be NMI source x86/platform/UV: Verify NMI action is valid, default is standard x86/platform/UV: Add basic CPU NMI health check x86/platform/UV: Add Support for UV4 Hubless NMIs x86/platform/UV: Add Support for UV4 Hubless systems x86/platform/UV: Clean up the UV APIC code x86/platform/intel-mid: Move watchdog registration to arch_initcall() x86/platform/intel-mid: Don't shadow error code of mp_map_gsi_to_irq() x86/platform/intel-mid: Allocate RTC interrupt for Merrifield x86/ioapic: Return suitable error code in mp_map_gsi_to_irq() x86/platform/UV: Fix 2 socket config problem x86/platform/UV: Fix panic with missing UVsystab support x86/platform/intel-mid: Enable RTC on Intel Merrifield x86/platform/intel: Remove PMIC GPIO block support x86/platform/intel-mid: Make intel_scu_device_register() static x86/platform/intel-mid: Enable GPIO keys on Merrifield x86/platform/intel-mid: Get rid of duplication of IPC handler ...
This commit is contained in:
Linus Torvalds
Коммит
c945d0227d
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@ -27,7 +27,6 @@ extern void intel_mid_pwr_power_off(void);
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extern int intel_mid_pwr_get_lss_id(struct pci_dev *pdev);
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extern int get_gpio_by_name(const char *name);
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extern void intel_scu_device_register(struct platform_device *pdev);
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extern int __init sfi_parse_mrtc(struct sfi_table_header *table);
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extern int __init sfi_parse_mtmr(struct sfi_table_header *table);
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extern int sfi_mrtc_num;
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@ -42,10 +41,8 @@ struct devs_id {
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char name[SFI_NAME_LEN + 1];
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u8 type;
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u8 delay;
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u8 msic;
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void *(*get_platform_data)(void *info);
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/* Custom handler for devices */
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void (*device_handler)(struct sfi_device_table_entry *pentry,
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struct devs_id *dev);
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};
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#define sfi_device(i) \
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@ -10,6 +10,7 @@ struct mm_struct;
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extern enum uv_system_type get_uv_system_type(void);
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extern int is_uv_system(void);
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extern int is_uv_hubless(void);
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extern void uv_cpu_init(void);
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extern void uv_nmi_init(void);
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extern void uv_system_init(void);
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@ -23,6 +24,7 @@ extern const struct cpumask *uv_flush_tlb_others(const struct cpumask *cpumask,
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static inline enum uv_system_type get_uv_system_type(void) { return UV_NONE; }
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static inline int is_uv_system(void) { return 0; }
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static inline int is_uv_hubless(void) { return 0; }
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static inline void uv_cpu_init(void) { }
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static inline void uv_system_init(void) { }
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static inline const struct cpumask *
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@ -772,6 +772,7 @@ static inline int uv_num_possible_blades(void)
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/* Per Hub NMI support */
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extern void uv_nmi_setup(void);
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extern void uv_nmi_setup_hubless(void);
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/* BMC sets a bit this MMR non-zero before sending an NMI */
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#define UVH_NMI_MMR UVH_SCRATCH5
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@ -799,6 +800,8 @@ struct uv_hub_nmi_s {
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atomic_t read_mmr_count; /* count of MMR reads */
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atomic_t nmi_count; /* count of true UV NMIs */
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unsigned long nmi_value; /* last value read from NMI MMR */
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bool hub_present; /* false means UV hubless system */
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bool pch_owner; /* indicates this hub owns PCH */
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};
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struct uv_cpu_nmi_s {
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@ -1107,12 +1107,12 @@ int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info)
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ioapic = mp_find_ioapic(gsi);
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if (ioapic < 0)
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return -1;
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return -ENODEV;
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pin = mp_find_ioapic_pin(ioapic, gsi);
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idx = find_irq_entry(ioapic, pin, mp_INT);
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if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
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return -1;
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return -ENODEV;
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return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info);
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}
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Разница между файлами не показана из-за своего большого размера
Загрузить разницу
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@ -1347,8 +1347,7 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus)
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pr_info("CPU0: ");
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print_cpu_info(&cpu_data(0));
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if (is_uv_system())
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uv_system_init();
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uv_system_init();
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set_mtrr_aps_delayed_init();
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@ -5,14 +5,12 @@ obj-$(subst m,y,$(CONFIG_MMC_SDHCI_PCI)) += platform_mrfld_sd.o
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# WiFi
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obj-$(subst m,y,$(CONFIG_BRCMFMAC_SDIO)) += platform_bcm43xx.o
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# IPC Devices
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obj-y += platform_ipc.o
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obj-$(subst m,y,$(CONFIG_MFD_INTEL_MSIC)) += platform_msic.o
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obj-$(subst m,y,$(CONFIG_SND_MFLD_MACHINE)) += platform_msic_audio.o
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obj-$(subst m,y,$(CONFIG_GPIO_MSIC)) += platform_msic_gpio.o
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obj-$(subst m,y,$(CONFIG_MFD_INTEL_MSIC)) += platform_msic_ocd.o
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obj-$(subst m,y,$(CONFIG_MFD_INTEL_MSIC)) += platform_msic_battery.o
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obj-$(subst m,y,$(CONFIG_INTEL_MID_POWER_BUTTON)) += platform_msic_power_btn.o
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obj-$(subst m,y,$(CONFIG_GPIO_INTEL_PMIC)) += platform_pmic_gpio.o
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obj-$(subst m,y,$(CONFIG_INTEL_MFLD_THERMAL)) += platform_msic_thermal.o
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# SPI Devices
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obj-$(subst m,y,$(CONFIG_SPI_SPIDEV)) += platform_mrfld_spidev.o
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@ -28,4 +26,5 @@ obj-$(subst m,y,$(CONFIG_GPIO_PCA953X)) += platform_pcal9555a.o
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obj-$(subst m,y,$(CONFIG_GPIO_PCA953X)) += platform_tca6416.o
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# MISC Devices
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obj-$(subst m,y,$(CONFIG_KEYBOARD_GPIO)) += platform_gpio_keys.o
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obj-$(subst m,y,$(CONFIG_RTC_DRV_CMOS)) += platform_mrfld_rtc.o
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obj-$(subst m,y,$(CONFIG_INTEL_MID_WATCHDOG)) += platform_mrfld_wdt.o
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@ -32,6 +32,9 @@ static struct gpio_keys_button gpio_button[] = {
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{SW_LID, -1, 1, "lid_switch", EV_SW, 0, 20},
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{KEY_VOLUMEUP, -1, 1, "vol_up", EV_KEY, 0, 20},
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{KEY_VOLUMEDOWN, -1, 1, "vol_down", EV_KEY, 0, 20},
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{KEY_MUTE, -1, 1, "mute_enable", EV_KEY, 0, 20},
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{KEY_VOLUMEUP, -1, 1, "volume_up", EV_KEY, 0, 20},
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{KEY_VOLUMEDOWN, -1, 1, "volume_down", EV_KEY, 0, 20},
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{KEY_CAMERA, -1, 1, "camera_full", EV_KEY, 0, 20},
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{KEY_CAMERA_FOCUS, -1, 1, "camera_half", EV_KEY, 0, 20},
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{SW_KEYPAD_SLIDE, -1, 1, "MagSw1", EV_SW, 0, 20},
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@ -1,68 +0,0 @@
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/*
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* platform_ipc.c: IPC platform library file
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*
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* (C) Copyright 2013 Intel Corporation
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* Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/sfi.h>
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#include <linux/gpio.h>
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#include <asm/intel-mid.h>
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#include "platform_ipc.h"
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void __init ipc_device_handler(struct sfi_device_table_entry *pentry,
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struct devs_id *dev)
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{
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struct platform_device *pdev;
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void *pdata = NULL;
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static struct resource res __initdata = {
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.name = "IRQ",
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.flags = IORESOURCE_IRQ,
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};
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pr_debug("IPC bus, name = %16.16s, irq = 0x%2x\n",
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pentry->name, pentry->irq);
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/*
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* We need to call platform init of IPC devices to fill misc_pdata
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* structure. It will be used in msic_init for initialization.
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*/
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if (dev != NULL)
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pdata = dev->get_platform_data(pentry);
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/*
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* On Medfield the platform device creation is handled by the MSIC
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* MFD driver so we don't need to do it here.
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*/
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if (intel_mid_has_msic())
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return;
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pdev = platform_device_alloc(pentry->name, 0);
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if (pdev == NULL) {
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pr_err("out of memory for SFI platform device '%s'.\n",
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pentry->name);
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return;
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}
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res.start = pentry->irq;
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platform_device_add_resources(pdev, &res, 1);
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pdev->dev.platform_data = pdata;
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intel_scu_device_register(pdev);
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}
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static const struct devs_id pmic_audio_dev_id __initconst = {
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.name = "pmic_audio",
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.type = SFI_DEV_TYPE_IPC,
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.delay = 1,
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.device_handler = &ipc_device_handler,
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};
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sfi_device(pmic_audio_dev_id);
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@ -1,18 +0,0 @@
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/*
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* platform_ipc.h: IPC platform library header file
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*
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* (C) Copyright 2013 Intel Corporation
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* Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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#ifndef _PLATFORM_IPC_H_
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#define _PLATFORM_IPC_H_
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void __init
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ipc_device_handler(struct sfi_device_table_entry *pentry, struct devs_id *dev);
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#endif
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@ -0,0 +1,48 @@
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/*
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* Intel Merrifield legacy RTC initialization file
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*
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* (C) Copyright 2017 Intel Corporation
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*
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* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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#include <linux/init.h>
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#include <asm/hw_irq.h>
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#include <asm/intel-mid.h>
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#include <asm/io_apic.h>
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#include <asm/time.h>
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#include <asm/x86_init.h>
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static int __init mrfld_legacy_rtc_alloc_irq(void)
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{
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struct irq_alloc_info info;
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int ret;
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if (!x86_platform.legacy.rtc)
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return -ENODEV;
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ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 1, 0);
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ret = mp_map_gsi_to_irq(RTC_IRQ, IOAPIC_MAP_ALLOC, &info);
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if (ret < 0) {
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pr_info("Failed to allocate RTC interrupt. Disabling RTC\n");
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x86_platform.legacy.rtc = 0;
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return ret;
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}
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return 0;
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}
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static int __init mrfld_legacy_rtc_init(void)
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{
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if (intel_mid_identify_cpu() != INTEL_MID_CPU_CHIP_TANGIER)
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return -ENODEV;
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return mrfld_legacy_rtc_alloc_irq();
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}
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arch_initcall(mrfld_legacy_rtc_init);
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@ -28,9 +28,9 @@ static struct platform_device wdt_dev = {
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static int tangier_probe(struct platform_device *pdev)
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{
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int gsi;
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struct irq_alloc_info info;
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struct intel_mid_wdt_pdata *pdata = pdev->dev.platform_data;
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int gsi, irq;
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if (!pdata)
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return -EINVAL;
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@ -38,10 +38,10 @@ static int tangier_probe(struct platform_device *pdev)
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/* IOAPIC builds identity mapping between GSI and IRQ on MID */
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gsi = pdata->irq;
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ioapic_set_alloc_attr(&info, cpu_to_node(0), 1, 0);
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if (mp_map_gsi_to_irq(gsi, IOAPIC_MAP_ALLOC, &info) <= 0) {
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dev_warn(&pdev->dev, "cannot find interrupt %d in ioapic\n",
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gsi);
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return -EINVAL;
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irq = mp_map_gsi_to_irq(gsi, IOAPIC_MAP_ALLOC, &info);
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if (irq < 0) {
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dev_warn(&pdev->dev, "cannot find interrupt %d in ioapic\n", gsi);
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return irq;
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}
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return 0;
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@ -82,4 +82,4 @@ static int __init register_mid_wdt(void)
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return 0;
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}
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rootfs_initcall(register_mid_wdt);
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arch_initcall(register_mid_wdt);
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|
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|
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@ -20,7 +20,6 @@
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#include <asm/intel-mid.h>
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#include "platform_msic.h"
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#include "platform_ipc.h"
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static void *msic_audio_platform_data(void *info)
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{
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@ -40,8 +39,8 @@ static const struct devs_id msic_audio_dev_id __initconst = {
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.name = "msic_audio",
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.type = SFI_DEV_TYPE_IPC,
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.delay = 1,
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.msic = 1,
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.get_platform_data = &msic_audio_platform_data,
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.device_handler = &ipc_device_handler,
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};
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|
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sfi_device(msic_audio_dev_id);
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|
|
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|
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@ -19,7 +19,6 @@
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#include <asm/intel-mid.h>
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|
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#include "platform_msic.h"
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#include "platform_ipc.h"
|
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|
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static void __init *msic_battery_platform_data(void *info)
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{
|
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|
|
@ -30,8 +29,8 @@ static const struct devs_id msic_battery_dev_id __initconst = {
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.name = "msic_battery",
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.type = SFI_DEV_TYPE_IPC,
|
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.delay = 1,
|
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.msic = 1,
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.get_platform_data = &msic_battery_platform_data,
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.device_handler = &ipc_device_handler,
|
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};
|
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|
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sfi_device(msic_battery_dev_id);
|
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|
|
|
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|
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@ -20,7 +20,6 @@
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#include <asm/intel-mid.h>
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|
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#include "platform_msic.h"
|
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#include "platform_ipc.h"
|
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|
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static void __init *msic_gpio_platform_data(void *info)
|
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{
|
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|
|
@ -41,8 +40,8 @@ static const struct devs_id msic_gpio_dev_id __initconst = {
|
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.name = "msic_gpio",
|
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.type = SFI_DEV_TYPE_IPC,
|
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.delay = 1,
|
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.msic = 1,
|
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.get_platform_data = &msic_gpio_platform_data,
|
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.device_handler = &ipc_device_handler,
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};
|
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|
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sfi_device(msic_gpio_dev_id);
|
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|
|
|
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|
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@ -20,7 +20,6 @@
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#include <asm/intel-mid.h>
|
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|
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#include "platform_msic.h"
|
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#include "platform_ipc.h"
|
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|
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static void __init *msic_ocd_platform_data(void *info)
|
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{
|
||||
|
|
@ -42,8 +41,8 @@ static const struct devs_id msic_ocd_dev_id __initconst = {
|
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.name = "msic_ocd",
|
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.type = SFI_DEV_TYPE_IPC,
|
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.delay = 1,
|
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.msic = 1,
|
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.get_platform_data = &msic_ocd_platform_data,
|
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.device_handler = &ipc_device_handler,
|
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};
|
||||
|
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sfi_device(msic_ocd_dev_id);
|
||||
|
|
|
|||
|
|
@ -18,7 +18,6 @@
|
|||
#include <asm/intel-mid.h>
|
||||
|
||||
#include "platform_msic.h"
|
||||
#include "platform_ipc.h"
|
||||
|
||||
static void __init *msic_power_btn_platform_data(void *info)
|
||||
{
|
||||
|
|
@ -29,8 +28,8 @@ static const struct devs_id msic_power_btn_dev_id __initconst = {
|
|||
.name = "msic_power_btn",
|
||||
.type = SFI_DEV_TYPE_IPC,
|
||||
.delay = 1,
|
||||
.msic = 1,
|
||||
.get_platform_data = &msic_power_btn_platform_data,
|
||||
.device_handler = &ipc_device_handler,
|
||||
};
|
||||
|
||||
sfi_device(msic_power_btn_dev_id);
|
||||
|
|
|
|||
|
|
@ -19,7 +19,6 @@
|
|||
#include <asm/intel-mid.h>
|
||||
|
||||
#include "platform_msic.h"
|
||||
#include "platform_ipc.h"
|
||||
|
||||
static void __init *msic_thermal_platform_data(void *info)
|
||||
{
|
||||
|
|
@ -30,8 +29,8 @@ static const struct devs_id msic_thermal_dev_id __initconst = {
|
|||
.name = "msic_thermal",
|
||||
.type = SFI_DEV_TYPE_IPC,
|
||||
.delay = 1,
|
||||
.msic = 1,
|
||||
.get_platform_data = &msic_thermal_platform_data,
|
||||
.device_handler = &ipc_device_handler,
|
||||
};
|
||||
|
||||
sfi_device(msic_thermal_dev_id);
|
||||
|
|
|
|||
|
|
@ -1,54 +0,0 @@
|
|||
/*
|
||||
* platform_pmic_gpio.c: PMIC GPIO platform data initialization file
|
||||
*
|
||||
* (C) Copyright 2013 Intel Corporation
|
||||
* Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* as published by the Free Software Foundation; version 2
|
||||
* of the License.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/scatterlist.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/sfi.h>
|
||||
#include <linux/intel_pmic_gpio.h>
|
||||
#include <asm/intel-mid.h>
|
||||
|
||||
#include "platform_ipc.h"
|
||||
|
||||
static void __init *pmic_gpio_platform_data(void *info)
|
||||
{
|
||||
static struct intel_pmic_gpio_platform_data pmic_gpio_pdata;
|
||||
int gpio_base = get_gpio_by_name("pmic_gpio_base");
|
||||
|
||||
if (gpio_base < 0)
|
||||
gpio_base = 64;
|
||||
pmic_gpio_pdata.gpio_base = gpio_base;
|
||||
pmic_gpio_pdata.irq_base = gpio_base + INTEL_MID_IRQ_OFFSET;
|
||||
pmic_gpio_pdata.gpiointr = 0xffffeff8;
|
||||
|
||||
return &pmic_gpio_pdata;
|
||||
}
|
||||
|
||||
static const struct devs_id pmic_gpio_spi_dev_id __initconst = {
|
||||
.name = "pmic_gpio",
|
||||
.type = SFI_DEV_TYPE_SPI,
|
||||
.delay = 1,
|
||||
.get_platform_data = &pmic_gpio_platform_data,
|
||||
};
|
||||
|
||||
static const struct devs_id pmic_gpio_ipc_dev_id __initconst = {
|
||||
.name = "pmic_gpio",
|
||||
.type = SFI_DEV_TYPE_IPC,
|
||||
.delay = 1,
|
||||
.get_platform_data = &pmic_gpio_platform_data,
|
||||
.device_handler = &ipc_device_handler
|
||||
};
|
||||
|
||||
sfi_device(pmic_gpio_spi_dev_id);
|
||||
sfi_device(pmic_gpio_ipc_dev_id);
|
||||
|
|
@ -91,6 +91,7 @@ static unsigned long __init tangier_calibrate_tsc(void)
|
|||
static void __init tangier_arch_setup(void)
|
||||
{
|
||||
x86_platform.calibrate_tsc = tangier_calibrate_tsc;
|
||||
x86_platform.legacy.rtc = 1;
|
||||
}
|
||||
|
||||
/* tangier arch ops */
|
||||
|
|
|
|||
|
|
@ -15,7 +15,6 @@
|
|||
#include <linux/interrupt.h>
|
||||
#include <linux/scatterlist.h>
|
||||
#include <linux/sfi.h>
|
||||
#include <linux/intel_pmic_gpio.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/skbuff.h>
|
||||
|
|
@ -226,7 +225,7 @@ int get_gpio_by_name(const char *name)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
void __init intel_scu_device_register(struct platform_device *pdev)
|
||||
static void __init intel_scu_ipc_device_register(struct platform_device *pdev)
|
||||
{
|
||||
if (ipc_next_dev == MAX_IPCDEVS)
|
||||
pr_err("too many SCU IPC devices");
|
||||
|
|
@ -335,10 +334,22 @@ static void __init sfi_handle_ipc_dev(struct sfi_device_table_entry *pentry,
|
|||
|
||||
pr_debug("IPC bus, name = %16.16s, irq = 0x%2x\n",
|
||||
pentry->name, pentry->irq);
|
||||
|
||||
/*
|
||||
* We need to call platform init of IPC devices to fill misc_pdata
|
||||
* structure. It will be used in msic_init for initialization.
|
||||
*/
|
||||
pdata = intel_mid_sfi_get_pdata(dev, pentry);
|
||||
if (IS_ERR(pdata))
|
||||
return;
|
||||
|
||||
/*
|
||||
* On Medfield the platform device creation is handled by the MSIC
|
||||
* MFD driver so we don't need to do it here.
|
||||
*/
|
||||
if (dev->msic && intel_mid_has_msic())
|
||||
return;
|
||||
|
||||
pdev = platform_device_alloc(pentry->name, 0);
|
||||
if (pdev == NULL) {
|
||||
pr_err("out of memory for SFI platform device '%s'.\n",
|
||||
|
|
@ -348,7 +359,10 @@ static void __init sfi_handle_ipc_dev(struct sfi_device_table_entry *pentry,
|
|||
install_irq_resource(pdev, pentry->irq);
|
||||
|
||||
pdev->dev.platform_data = pdata;
|
||||
platform_device_add(pdev);
|
||||
if (dev->delay)
|
||||
intel_scu_ipc_device_register(pdev);
|
||||
else
|
||||
platform_device_add(pdev);
|
||||
}
|
||||
|
||||
static void __init sfi_handle_spi_dev(struct sfi_device_table_entry *pentry,
|
||||
|
|
@ -503,27 +517,23 @@ static int __init sfi_parse_devs(struct sfi_table_header *table)
|
|||
if (!dev)
|
||||
continue;
|
||||
|
||||
if (dev->device_handler) {
|
||||
dev->device_handler(pentry, dev);
|
||||
} else {
|
||||
switch (pentry->type) {
|
||||
case SFI_DEV_TYPE_IPC:
|
||||
sfi_handle_ipc_dev(pentry, dev);
|
||||
break;
|
||||
case SFI_DEV_TYPE_SPI:
|
||||
sfi_handle_spi_dev(pentry, dev);
|
||||
break;
|
||||
case SFI_DEV_TYPE_I2C:
|
||||
sfi_handle_i2c_dev(pentry, dev);
|
||||
break;
|
||||
case SFI_DEV_TYPE_SD:
|
||||
sfi_handle_sd_dev(pentry, dev);
|
||||
break;
|
||||
case SFI_DEV_TYPE_UART:
|
||||
case SFI_DEV_TYPE_HSI:
|
||||
default:
|
||||
break;
|
||||
}
|
||||
switch (pentry->type) {
|
||||
case SFI_DEV_TYPE_IPC:
|
||||
sfi_handle_ipc_dev(pentry, dev);
|
||||
break;
|
||||
case SFI_DEV_TYPE_SPI:
|
||||
sfi_handle_spi_dev(pentry, dev);
|
||||
break;
|
||||
case SFI_DEV_TYPE_I2C:
|
||||
sfi_handle_i2c_dev(pentry, dev);
|
||||
break;
|
||||
case SFI_DEV_TYPE_SD:
|
||||
sfi_handle_sd_dev(pentry, dev);
|
||||
break;
|
||||
case SFI_DEV_TYPE_UART:
|
||||
case SFI_DEV_TYPE_HSI:
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -45,8 +45,8 @@
|
|||
*
|
||||
* Handle system-wide NMI events generated by the global 'power nmi' command.
|
||||
*
|
||||
* Basic operation is to field the NMI interrupt on each cpu and wait
|
||||
* until all cpus have arrived into the nmi handler. If some cpus do not
|
||||
* Basic operation is to field the NMI interrupt on each CPU and wait
|
||||
* until all CPU's have arrived into the nmi handler. If some CPU's do not
|
||||
* make it into the handler, try and force them in with the IPI(NMI) signal.
|
||||
*
|
||||
* We also have to lessen UV Hub MMR accesses as much as possible as this
|
||||
|
|
@ -56,7 +56,7 @@
|
|||
* To do this we register our primary NMI notifier on the NMI_UNKNOWN
|
||||
* chain. This reduces the number of false NMI calls when the perf
|
||||
* tools are running which generate an enormous number of NMIs per
|
||||
* second (~4M/s for 1024 cpu threads). Our secondary NMI handler is
|
||||
* second (~4M/s for 1024 CPU threads). Our secondary NMI handler is
|
||||
* very short as it only checks that if it has been "pinged" with the
|
||||
* IPI(NMI) signal as mentioned above, and does not read the UV Hub's MMR.
|
||||
*
|
||||
|
|
@ -65,8 +65,20 @@
|
|||
static struct uv_hub_nmi_s **uv_hub_nmi_list;
|
||||
|
||||
DEFINE_PER_CPU(struct uv_cpu_nmi_s, uv_cpu_nmi);
|
||||
EXPORT_PER_CPU_SYMBOL_GPL(uv_cpu_nmi);
|
||||
|
||||
/* UV hubless values */
|
||||
#define NMI_CONTROL_PORT 0x70
|
||||
#define NMI_DUMMY_PORT 0x71
|
||||
#define PAD_OWN_GPP_D_0 0x2c
|
||||
#define GPI_NMI_STS_GPP_D_0 0x164
|
||||
#define GPI_NMI_ENA_GPP_D_0 0x174
|
||||
#define STS_GPP_D_0_MASK 0x1
|
||||
#define PAD_CFG_DW0_GPP_D_0 0x4c0
|
||||
#define GPIROUTNMI (1ul << 17)
|
||||
#define PCH_PCR_GPIO_1_BASE 0xfdae0000ul
|
||||
#define PCH_PCR_GPIO_ADDRESS(offset) (int *)((u64)(pch_base) | (u64)(offset))
|
||||
|
||||
static u64 *pch_base;
|
||||
static unsigned long nmi_mmr;
|
||||
static unsigned long nmi_mmr_clear;
|
||||
static unsigned long nmi_mmr_pending;
|
||||
|
|
@ -100,7 +112,7 @@ static int param_get_local64(char *buffer, const struct kernel_param *kp)
|
|||
|
||||
static int param_set_local64(const char *val, const struct kernel_param *kp)
|
||||
{
|
||||
/* clear on any write */
|
||||
/* Clear on any write */
|
||||
local64_set((local64_t *)kp->arg, 0);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -144,16 +156,80 @@ module_param_named(wait_count, uv_nmi_wait_count, int, 0644);
|
|||
static int uv_nmi_retry_count = 500;
|
||||
module_param_named(retry_count, uv_nmi_retry_count, int, 0644);
|
||||
|
||||
/*
|
||||
* Valid NMI Actions:
|
||||
* "dump" - dump process stack for each cpu
|
||||
* "ips" - dump IP info for each cpu
|
||||
* "kdump" - do crash dump
|
||||
* "kdb" - enter KDB (default)
|
||||
* "kgdb" - enter KGDB
|
||||
*/
|
||||
static char uv_nmi_action[8] = "kdb";
|
||||
module_param_string(action, uv_nmi_action, sizeof(uv_nmi_action), 0644);
|
||||
static bool uv_pch_intr_enable = true;
|
||||
static bool uv_pch_intr_now_enabled;
|
||||
module_param_named(pch_intr_enable, uv_pch_intr_enable, bool, 0644);
|
||||
|
||||
static bool uv_pch_init_enable = true;
|
||||
module_param_named(pch_init_enable, uv_pch_init_enable, bool, 0644);
|
||||
|
||||
static int uv_nmi_debug;
|
||||
module_param_named(debug, uv_nmi_debug, int, 0644);
|
||||
|
||||
#define nmi_debug(fmt, ...) \
|
||||
do { \
|
||||
if (uv_nmi_debug) \
|
||||
pr_info(fmt, ##__VA_ARGS__); \
|
||||
} while (0)
|
||||
|
||||
/* Valid NMI Actions */
|
||||
#define ACTION_LEN 16
|
||||
static struct nmi_action {
|
||||
char *action;
|
||||
char *desc;
|
||||
} valid_acts[] = {
|
||||
{ "kdump", "do kernel crash dump" },
|
||||
{ "dump", "dump process stack for each cpu" },
|
||||
{ "ips", "dump Inst Ptr info for each cpu" },
|
||||
{ "kdb", "enter KDB (needs kgdboc= assignment)" },
|
||||
{ "kgdb", "enter KGDB (needs gdb target remote)" },
|
||||
{ "health", "check if CPUs respond to NMI" },
|
||||
};
|
||||
typedef char action_t[ACTION_LEN];
|
||||
static action_t uv_nmi_action = { "dump" };
|
||||
|
||||
static int param_get_action(char *buffer, const struct kernel_param *kp)
|
||||
{
|
||||
return sprintf(buffer, "%s\n", uv_nmi_action);
|
||||
}
|
||||
|
||||
static int param_set_action(const char *val, const struct kernel_param *kp)
|
||||
{
|
||||
int i;
|
||||
int n = ARRAY_SIZE(valid_acts);
|
||||
char arg[ACTION_LEN], *p;
|
||||
|
||||
/* (remove possible '\n') */
|
||||
strncpy(arg, val, ACTION_LEN - 1);
|
||||
arg[ACTION_LEN - 1] = '\0';
|
||||
p = strchr(arg, '\n');
|
||||
if (p)
|
||||
*p = '\0';
|
||||
|
||||
for (i = 0; i < n; i++)
|
||||
if (!strcmp(arg, valid_acts[i].action))
|
||||
break;
|
||||
|
||||
if (i < n) {
|
||||
strcpy(uv_nmi_action, arg);
|
||||
pr_info("UV: New NMI action:%s\n", uv_nmi_action);
|
||||
return 0;
|
||||
}
|
||||
|
||||
pr_err("UV: Invalid NMI action:%s, valid actions are:\n", arg);
|
||||
for (i = 0; i < n; i++)
|
||||
pr_err("UV: %-8s - %s\n",
|
||||
valid_acts[i].action, valid_acts[i].desc);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static const struct kernel_param_ops param_ops_action = {
|
||||
.get = param_get_action,
|
||||
.set = param_set_action,
|
||||
};
|
||||
#define param_check_action(name, p) __param_check(name, p, action_t)
|
||||
|
||||
module_param_named(action, uv_nmi_action, action, 0644);
|
||||
|
||||
static inline bool uv_nmi_action_is(const char *action)
|
||||
{
|
||||
|
|
@ -192,8 +268,200 @@ static inline void uv_local_mmr_clear_nmi(void)
|
|||
}
|
||||
|
||||
/*
|
||||
* If first cpu in on this hub, set hub_nmi "in_nmi" and "owner" values and
|
||||
* return true. If first cpu in on the system, set global "in_nmi" flag.
|
||||
* UV hubless NMI handler functions
|
||||
*/
|
||||
static inline void uv_reassert_nmi(void)
|
||||
{
|
||||
/* (from arch/x86/include/asm/mach_traps.h) */
|
||||
outb(0x8f, NMI_CONTROL_PORT);
|
||||
inb(NMI_DUMMY_PORT); /* dummy read */
|
||||
outb(0x0f, NMI_CONTROL_PORT);
|
||||
inb(NMI_DUMMY_PORT); /* dummy read */
|
||||
}
|
||||
|
||||
static void uv_init_hubless_pch_io(int offset, int mask, int data)
|
||||
{
|
||||
int *addr = PCH_PCR_GPIO_ADDRESS(offset);
|
||||
int readd = readl(addr);
|
||||
|
||||
if (mask) { /* OR in new data */
|
||||
int writed = (readd & ~mask) | data;
|
||||
|
||||
nmi_debug("UV:PCH: %p = %x & %x | %x (%x)\n",
|
||||
addr, readd, ~mask, data, writed);
|
||||
writel(writed, addr);
|
||||
} else if (readd & data) { /* clear status bit */
|
||||
nmi_debug("UV:PCH: %p = %x\n", addr, data);
|
||||
writel(data, addr);
|
||||
}
|
||||
|
||||
(void)readl(addr); /* flush write data */
|
||||
}
|
||||
|
||||
static void uv_nmi_setup_hubless_intr(void)
|
||||
{
|
||||
uv_pch_intr_now_enabled = uv_pch_intr_enable;
|
||||
|
||||
uv_init_hubless_pch_io(
|
||||
PAD_CFG_DW0_GPP_D_0, GPIROUTNMI,
|
||||
uv_pch_intr_now_enabled ? GPIROUTNMI : 0);
|
||||
|
||||
nmi_debug("UV:NMI: GPP_D_0 interrupt %s\n",
|
||||
uv_pch_intr_now_enabled ? "enabled" : "disabled");
|
||||
}
|
||||
|
||||
static struct init_nmi {
|
||||
unsigned int offset;
|
||||
unsigned int mask;
|
||||
unsigned int data;
|
||||
} init_nmi[] = {
|
||||
{ /* HOSTSW_OWN_GPP_D_0 */
|
||||
.offset = 0x84,
|
||||
.mask = 0x1,
|
||||
.data = 0x0, /* ACPI Mode */
|
||||
},
|
||||
|
||||
/* Clear status: */
|
||||
{ /* GPI_INT_STS_GPP_D_0 */
|
||||
.offset = 0x104,
|
||||
.mask = 0x0,
|
||||
.data = 0x1, /* Clear Status */
|
||||
},
|
||||
{ /* GPI_GPE_STS_GPP_D_0 */
|
||||
.offset = 0x124,
|
||||
.mask = 0x0,
|
||||
.data = 0x1, /* Clear Status */
|
||||
},
|
||||
{ /* GPI_SMI_STS_GPP_D_0 */
|
||||
.offset = 0x144,
|
||||
.mask = 0x0,
|
||||
.data = 0x1, /* Clear Status */
|
||||
},
|
||||
{ /* GPI_NMI_STS_GPP_D_0 */
|
||||
.offset = 0x164,
|
||||
.mask = 0x0,
|
||||
.data = 0x1, /* Clear Status */
|
||||
},
|
||||
|
||||
/* Disable interrupts: */
|
||||
{ /* GPI_INT_EN_GPP_D_0 */
|
||||
.offset = 0x114,
|
||||
.mask = 0x1,
|
||||
.data = 0x0, /* Disable interrupt generation */
|
||||
},
|
||||
{ /* GPI_GPE_EN_GPP_D_0 */
|
||||
.offset = 0x134,
|
||||
.mask = 0x1,
|
||||
.data = 0x0, /* Disable interrupt generation */
|
||||
},
|
||||
{ /* GPI_SMI_EN_GPP_D_0 */
|
||||
.offset = 0x154,
|
||||
.mask = 0x1,
|
||||
.data = 0x0, /* Disable interrupt generation */
|
||||
},
|
||||
{ /* GPI_NMI_EN_GPP_D_0 */
|
||||
.offset = 0x174,
|
||||
.mask = 0x1,
|
||||
.data = 0x0, /* Disable interrupt generation */
|
||||
},
|
||||
|
||||
/* Setup GPP_D_0 Pad Config: */
|
||||
{ /* PAD_CFG_DW0_GPP_D_0 */
|
||||
.offset = 0x4c0,
|
||||
.mask = 0xffffffff,
|
||||
.data = 0x82020100,
|
||||
/*
|
||||
* 31:30 Pad Reset Config (PADRSTCFG): = 2h # PLTRST# (default)
|
||||
*
|
||||
* 29 RX Pad State Select (RXPADSTSEL): = 0 # Raw RX pad state directly
|
||||
* from RX buffer (default)
|
||||
*
|
||||
* 28 RX Raw Override to '1' (RXRAW1): = 0 # No Override
|
||||
*
|
||||
* 26:25 RX Level/Edge Configuration (RXEVCFG):
|
||||
* = 0h # Level
|
||||
* = 1h # Edge
|
||||
*
|
||||
* 23 RX Invert (RXINV): = 0 # No Inversion (signal active high)
|
||||
*
|
||||
* 20 GPIO Input Route IOxAPIC (GPIROUTIOXAPIC):
|
||||
* = 0 # Routing does not cause peripheral IRQ...
|
||||
* # (we want an NMI not an IRQ)
|
||||
*
|
||||
* 19 GPIO Input Route SCI (GPIROUTSCI): = 0 # Routing does not cause SCI.
|
||||
* 18 GPIO Input Route SMI (GPIROUTSMI): = 0 # Routing does not cause SMI.
|
||||
* 17 GPIO Input Route NMI (GPIROUTNMI): = 1 # Routing can cause NMI.
|
||||
*
|
||||
* 11:10 Pad Mode (PMODE1/0): = 0h = GPIO control the Pad.
|
||||
* 9 GPIO RX Disable (GPIORXDIS):
|
||||
* = 0 # Enable the input buffer (active low enable)
|
||||
*
|
||||
* 8 GPIO TX Disable (GPIOTXDIS):
|
||||
* = 1 # Disable the output buffer; i.e. Hi-Z
|
||||
*
|
||||
* 1 GPIO RX State (GPIORXSTATE): This is the current internal RX pad state..
|
||||
* 0 GPIO TX State (GPIOTXSTATE):
|
||||
* = 0 # (Leave at default)
|
||||
*/
|
||||
},
|
||||
|
||||
/* Pad Config DW1 */
|
||||
{ /* PAD_CFG_DW1_GPP_D_0 */
|
||||
.offset = 0x4c4,
|
||||
.mask = 0x3c00,
|
||||
.data = 0, /* Termination = none (default) */
|
||||
},
|
||||
};
|
||||
|
||||
static void uv_init_hubless_pch_d0(void)
|
||||
{
|
||||
int i, read;
|
||||
|
||||
read = *PCH_PCR_GPIO_ADDRESS(PAD_OWN_GPP_D_0);
|
||||
if (read != 0) {
|
||||
pr_info("UV: Hubless NMI already configured\n");
|
||||
return;
|
||||
}
|
||||
|
||||
nmi_debug("UV: Initializing UV Hubless NMI on PCH\n");
|
||||
for (i = 0; i < ARRAY_SIZE(init_nmi); i++) {
|
||||
uv_init_hubless_pch_io(init_nmi[i].offset,
|
||||
init_nmi[i].mask,
|
||||
init_nmi[i].data);
|
||||
}
|
||||
}
|
||||
|
||||
static int uv_nmi_test_hubless(struct uv_hub_nmi_s *hub_nmi)
|
||||
{
|
||||
int *pstat = PCH_PCR_GPIO_ADDRESS(GPI_NMI_STS_GPP_D_0);
|
||||
int status = *pstat;
|
||||
|
||||
hub_nmi->nmi_value = status;
|
||||
atomic_inc(&hub_nmi->read_mmr_count);
|
||||
|
||||
if (!(status & STS_GPP_D_0_MASK)) /* Not a UV external NMI */
|
||||
return 0;
|
||||
|
||||
*pstat = STS_GPP_D_0_MASK; /* Is a UV NMI: clear GPP_D_0 status */
|
||||
(void)*pstat; /* Flush write */
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int uv_test_nmi(struct uv_hub_nmi_s *hub_nmi)
|
||||
{
|
||||
if (hub_nmi->hub_present)
|
||||
return uv_nmi_test_mmr(hub_nmi);
|
||||
|
||||
if (hub_nmi->pch_owner) /* Only PCH owner can check status */
|
||||
return uv_nmi_test_hubless(hub_nmi);
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* If first CPU in on this hub, set hub_nmi "in_nmi" and "owner" values and
|
||||
* return true. If first CPU in on the system, set global "in_nmi" flag.
|
||||
*/
|
||||
static int uv_set_in_nmi(int cpu, struct uv_hub_nmi_s *hub_nmi)
|
||||
{
|
||||
|
|
@ -214,6 +482,7 @@ static int uv_check_nmi(struct uv_hub_nmi_s *hub_nmi)
|
|||
{
|
||||
int cpu = smp_processor_id();
|
||||
int nmi = 0;
|
||||
int nmi_detected = 0;
|
||||
|
||||
local64_inc(&uv_nmi_count);
|
||||
this_cpu_inc(uv_cpu_nmi.queries);
|
||||
|
|
@ -224,35 +493,48 @@ static int uv_check_nmi(struct uv_hub_nmi_s *hub_nmi)
|
|||
break;
|
||||
|
||||
if (raw_spin_trylock(&hub_nmi->nmi_lock)) {
|
||||
nmi_detected = uv_test_nmi(hub_nmi);
|
||||
|
||||
/* check hub MMR NMI flag */
|
||||
if (uv_nmi_test_mmr(hub_nmi)) {
|
||||
/* Check flag for UV external NMI */
|
||||
if (nmi_detected > 0) {
|
||||
uv_set_in_nmi(cpu, hub_nmi);
|
||||
nmi = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
/* MMR NMI flag is clear */
|
||||
/* A non-PCH node in a hubless system waits for NMI */
|
||||
else if (nmi_detected < 0)
|
||||
goto slave_wait;
|
||||
|
||||
/* MMR/PCH NMI flag is clear */
|
||||
raw_spin_unlock(&hub_nmi->nmi_lock);
|
||||
|
||||
} else {
|
||||
/* wait a moment for the hub nmi locker to set flag */
|
||||
cpu_relax();
|
||||
|
||||
/* Wait a moment for the HUB NMI locker to set flag */
|
||||
slave_wait: cpu_relax();
|
||||
udelay(uv_nmi_slave_delay);
|
||||
|
||||
/* re-check hub in_nmi flag */
|
||||
/* Re-check hub in_nmi flag */
|
||||
nmi = atomic_read(&hub_nmi->in_nmi);
|
||||
if (nmi)
|
||||
break;
|
||||
}
|
||||
|
||||
/* check if this BMC missed setting the MMR NMI flag */
|
||||
/*
|
||||
* Check if this BMC missed setting the MMR NMI flag (or)
|
||||
* UV hubless system where only PCH owner can check flag
|
||||
*/
|
||||
if (!nmi) {
|
||||
nmi = atomic_read(&uv_in_nmi);
|
||||
if (nmi)
|
||||
uv_set_in_nmi(cpu, hub_nmi);
|
||||
}
|
||||
|
||||
/* If we're holding the hub lock, release it now */
|
||||
if (nmi_detected < 0)
|
||||
raw_spin_unlock(&hub_nmi->nmi_lock);
|
||||
|
||||
} while (0);
|
||||
|
||||
if (!nmi)
|
||||
|
|
@ -269,12 +551,15 @@ static inline void uv_clear_nmi(int cpu)
|
|||
if (cpu == atomic_read(&hub_nmi->cpu_owner)) {
|
||||
atomic_set(&hub_nmi->cpu_owner, -1);
|
||||
atomic_set(&hub_nmi->in_nmi, 0);
|
||||
uv_local_mmr_clear_nmi();
|
||||
if (hub_nmi->hub_present)
|
||||
uv_local_mmr_clear_nmi();
|
||||
else
|
||||
uv_reassert_nmi();
|
||||
raw_spin_unlock(&hub_nmi->nmi_lock);
|
||||
}
|
||||
}
|
||||
|
||||
/* Ping non-responding cpus attemping to force them into the NMI handler */
|
||||
/* Ping non-responding CPU's attemping to force them into the NMI handler */
|
||||
static void uv_nmi_nr_cpus_ping(void)
|
||||
{
|
||||
int cpu;
|
||||
|
|
@ -285,7 +570,7 @@ static void uv_nmi_nr_cpus_ping(void)
|
|||
apic->send_IPI_mask(uv_nmi_cpu_mask, APIC_DM_NMI);
|
||||
}
|
||||
|
||||
/* Clean up flags for cpus that ignored both NMI and ping */
|
||||
/* Clean up flags for CPU's that ignored both NMI and ping */
|
||||
static void uv_nmi_cleanup_mask(void)
|
||||
{
|
||||
int cpu;
|
||||
|
|
@ -297,11 +582,12 @@ static void uv_nmi_cleanup_mask(void)
|
|||
}
|
||||
}
|
||||
|
||||
/* Loop waiting as cpus enter nmi handler */
|
||||
/* Loop waiting as CPU's enter NMI handler */
|
||||
static int uv_nmi_wait_cpus(int first)
|
||||
{
|
||||
int i, j, k, n = num_online_cpus();
|
||||
int last_k = 0, waiting = 0;
|
||||
int cpu = smp_processor_id();
|
||||
|
||||
if (first) {
|
||||
cpumask_copy(uv_nmi_cpu_mask, cpu_online_mask);
|
||||
|
|
@ -310,6 +596,12 @@ static int uv_nmi_wait_cpus(int first)
|
|||
k = n - cpumask_weight(uv_nmi_cpu_mask);
|
||||
}
|
||||
|
||||
/* PCH NMI causes only one CPU to respond */
|
||||
if (first && uv_pch_intr_now_enabled) {
|
||||
cpumask_clear_cpu(cpu, uv_nmi_cpu_mask);
|
||||
return n - k - 1;
|
||||
}
|
||||
|
||||
udelay(uv_nmi_initial_delay);
|
||||
for (i = 0; i < uv_nmi_retry_count; i++) {
|
||||
int loop_delay = uv_nmi_loop_delay;
|
||||
|
|
@ -325,13 +617,13 @@ static int uv_nmi_wait_cpus(int first)
|
|||
k = n;
|
||||
break;
|
||||
}
|
||||
if (last_k != k) { /* abort if no new cpus coming in */
|
||||
if (last_k != k) { /* abort if no new CPU's coming in */
|
||||
last_k = k;
|
||||
waiting = 0;
|
||||
} else if (++waiting > uv_nmi_wait_count)
|
||||
break;
|
||||
|
||||
/* extend delay if waiting only for cpu 0 */
|
||||
/* Extend delay if waiting only for CPU 0: */
|
||||
if (waiting && (n - k) == 1 &&
|
||||
cpumask_test_cpu(0, uv_nmi_cpu_mask))
|
||||
loop_delay *= 100;
|
||||
|
|
@ -342,29 +634,29 @@ static int uv_nmi_wait_cpus(int first)
|
|||
return n - k;
|
||||
}
|
||||
|
||||
/* Wait until all slave cpus have entered UV NMI handler */
|
||||
/* Wait until all slave CPU's have entered UV NMI handler */
|
||||
static void uv_nmi_wait(int master)
|
||||
{
|
||||
/* indicate this cpu is in */
|
||||
/* Indicate this CPU is in: */
|
||||
this_cpu_write(uv_cpu_nmi.state, UV_NMI_STATE_IN);
|
||||
|
||||
/* if not the first cpu in (the master), then we are a slave cpu */
|
||||
/* If not the first CPU in (the master), then we are a slave CPU */
|
||||
if (!master)
|
||||
return;
|
||||
|
||||
do {
|
||||
/* wait for all other cpus to gather here */
|
||||
/* Wait for all other CPU's to gather here */
|
||||
if (!uv_nmi_wait_cpus(1))
|
||||
break;
|
||||
|
||||
/* if not all made it in, send IPI NMI to them */
|
||||
pr_alert("UV: Sending NMI IPI to %d non-responding CPUs: %*pbl\n",
|
||||
/* If not all made it in, send IPI NMI to them */
|
||||
pr_alert("UV: Sending NMI IPI to %d CPUs: %*pbl\n",
|
||||
cpumask_weight(uv_nmi_cpu_mask),
|
||||
cpumask_pr_args(uv_nmi_cpu_mask));
|
||||
|
||||
uv_nmi_nr_cpus_ping();
|
||||
|
||||
/* if all cpus are in, then done */
|
||||
/* If all CPU's are in, then done */
|
||||
if (!uv_nmi_wait_cpus(0))
|
||||
break;
|
||||
|
||||
|
|
@ -416,7 +708,7 @@ static void uv_nmi_dump_state_cpu(int cpu, struct pt_regs *regs)
|
|||
this_cpu_write(uv_cpu_nmi.state, UV_NMI_STATE_DUMP_DONE);
|
||||
}
|
||||
|
||||
/* Trigger a slave cpu to dump it's state */
|
||||
/* Trigger a slave CPU to dump it's state */
|
||||
static void uv_nmi_trigger_dump(int cpu)
|
||||
{
|
||||
int retry = uv_nmi_trigger_delay;
|
||||
|
|
@ -437,7 +729,7 @@ static void uv_nmi_trigger_dump(int cpu)
|
|||
uv_cpu_nmi_per(cpu).state = UV_NMI_STATE_DUMP_DONE;
|
||||
}
|
||||
|
||||
/* Wait until all cpus ready to exit */
|
||||
/* Wait until all CPU's ready to exit */
|
||||
static void uv_nmi_sync_exit(int master)
|
||||
{
|
||||
atomic_dec(&uv_nmi_cpus_in_nmi);
|
||||
|
|
@ -451,7 +743,23 @@ static void uv_nmi_sync_exit(int master)
|
|||
}
|
||||
}
|
||||
|
||||
/* Walk through cpu list and dump state of each */
|
||||
/* Current "health" check is to check which CPU's are responsive */
|
||||
static void uv_nmi_action_health(int cpu, struct pt_regs *regs, int master)
|
||||
{
|
||||
if (master) {
|
||||
int in = atomic_read(&uv_nmi_cpus_in_nmi);
|
||||
int out = num_online_cpus() - in;
|
||||
|
||||
pr_alert("UV: NMI CPU health check (non-responding:%d)\n", out);
|
||||
atomic_set(&uv_nmi_slave_continue, SLAVE_EXIT);
|
||||
} else {
|
||||
while (!atomic_read(&uv_nmi_slave_continue))
|
||||
cpu_relax();
|
||||
}
|
||||
uv_nmi_sync_exit(master);
|
||||
}
|
||||
|
||||
/* Walk through CPU list and dump state of each */
|
||||
static void uv_nmi_dump_state(int cpu, struct pt_regs *regs, int master)
|
||||
{
|
||||
if (master) {
|
||||
|
|
@ -538,7 +846,7 @@ static inline int uv_nmi_kdb_reason(void)
|
|||
#else /* !CONFIG_KGDB_KDB */
|
||||
static inline int uv_nmi_kdb_reason(void)
|
||||
{
|
||||
/* Insure user is expecting to attach gdb remote */
|
||||
/* Ensure user is expecting to attach gdb remote */
|
||||
if (uv_nmi_action_is("kgdb"))
|
||||
return 0;
|
||||
|
||||
|
|
@ -563,7 +871,7 @@ static void uv_call_kgdb_kdb(int cpu, struct pt_regs *regs, int master)
|
|||
if (reason < 0)
|
||||
return;
|
||||
|
||||
/* call KGDB NMI handler as MASTER */
|
||||
/* Call KGDB NMI handler as MASTER */
|
||||
ret = kgdb_nmicallin(cpu, X86_TRAP_NMI, regs, reason,
|
||||
&uv_nmi_slave_continue);
|
||||
if (ret) {
|
||||
|
|
@ -571,7 +879,7 @@ static void uv_call_kgdb_kdb(int cpu, struct pt_regs *regs, int master)
|
|||
atomic_set(&uv_nmi_slave_continue, SLAVE_EXIT);
|
||||
}
|
||||
} else {
|
||||
/* wait for KGDB signal that it's ready for slaves to enter */
|
||||
/* Wait for KGDB signal that it's ready for slaves to enter */
|
||||
int sig;
|
||||
|
||||
do {
|
||||
|
|
@ -579,7 +887,7 @@ static void uv_call_kgdb_kdb(int cpu, struct pt_regs *regs, int master)
|
|||
sig = atomic_read(&uv_nmi_slave_continue);
|
||||
} while (!sig);
|
||||
|
||||
/* call KGDB as slave */
|
||||
/* Call KGDB as slave */
|
||||
if (sig == SLAVE_CONTINUE)
|
||||
kgdb_nmicallback(cpu, regs);
|
||||
}
|
||||
|
|
@ -623,18 +931,23 @@ int uv_handle_nmi(unsigned int reason, struct pt_regs *regs)
|
|||
strncpy(uv_nmi_action, "dump", strlen(uv_nmi_action));
|
||||
}
|
||||
|
||||
/* Pause as all cpus enter the NMI handler */
|
||||
/* Pause as all CPU's enter the NMI handler */
|
||||
uv_nmi_wait(master);
|
||||
|
||||
/* Dump state of each cpu */
|
||||
if (uv_nmi_action_is("ips") || uv_nmi_action_is("dump"))
|
||||
/* Process actions other than "kdump": */
|
||||
if (uv_nmi_action_is("health")) {
|
||||
uv_nmi_action_health(cpu, regs, master);
|
||||
} else if (uv_nmi_action_is("ips") || uv_nmi_action_is("dump")) {
|
||||
uv_nmi_dump_state(cpu, regs, master);
|
||||
|
||||
/* Call KGDB/KDB if enabled */
|
||||
else if (uv_nmi_action_is("kdb") || uv_nmi_action_is("kgdb"))
|
||||
} else if (uv_nmi_action_is("kdb") || uv_nmi_action_is("kgdb")) {
|
||||
uv_call_kgdb_kdb(cpu, regs, master);
|
||||
} else {
|
||||
if (master)
|
||||
pr_alert("UV: unknown NMI action: %s\n", uv_nmi_action);
|
||||
uv_nmi_sync_exit(master);
|
||||
}
|
||||
|
||||
/* Clear per_cpu "in nmi" flag */
|
||||
/* Clear per_cpu "in_nmi" flag */
|
||||
this_cpu_write(uv_cpu_nmi.state, UV_NMI_STATE_OUT);
|
||||
|
||||
/* Clear MMR NMI flag on each hub */
|
||||
|
|
@ -648,6 +961,7 @@ int uv_handle_nmi(unsigned int reason, struct pt_regs *regs)
|
|||
atomic_set(&uv_nmi_cpu, -1);
|
||||
atomic_set(&uv_in_nmi, 0);
|
||||
atomic_set(&uv_nmi_kexec_failed, 0);
|
||||
atomic_set(&uv_nmi_slave_continue, SLAVE_CLEAR);
|
||||
}
|
||||
|
||||
uv_nmi_touch_watchdogs();
|
||||
|
|
@ -657,7 +971,7 @@ int uv_handle_nmi(unsigned int reason, struct pt_regs *regs)
|
|||
}
|
||||
|
||||
/*
|
||||
* NMI handler for pulling in CPUs when perf events are grabbing our NMI
|
||||
* NMI handler for pulling in CPU's when perf events are grabbing our NMI
|
||||
*/
|
||||
static int uv_handle_nmi_ping(unsigned int reason, struct pt_regs *regs)
|
||||
{
|
||||
|
|
@ -690,35 +1004,62 @@ void uv_nmi_init(void)
|
|||
unsigned int value;
|
||||
|
||||
/*
|
||||
* Unmask NMI on all cpus
|
||||
* Unmask NMI on all CPU's
|
||||
*/
|
||||
value = apic_read(APIC_LVT1) | APIC_DM_NMI;
|
||||
value &= ~APIC_LVT_MASKED;
|
||||
apic_write(APIC_LVT1, value);
|
||||
}
|
||||
|
||||
void uv_nmi_setup(void)
|
||||
/* Setup HUB NMI info */
|
||||
void __init uv_nmi_setup_common(bool hubbed)
|
||||
{
|
||||
int size = sizeof(void *) * (1 << NODES_SHIFT);
|
||||
int cpu, nid;
|
||||
int cpu;
|
||||
|
||||
/* Setup hub nmi info */
|
||||
uv_nmi_setup_mmrs();
|
||||
uv_hub_nmi_list = kzalloc(size, GFP_KERNEL);
|
||||
pr_info("UV: NMI hub list @ 0x%p (%d)\n", uv_hub_nmi_list, size);
|
||||
nmi_debug("UV: NMI hub list @ 0x%p (%d)\n", uv_hub_nmi_list, size);
|
||||
BUG_ON(!uv_hub_nmi_list);
|
||||
size = sizeof(struct uv_hub_nmi_s);
|
||||
for_each_present_cpu(cpu) {
|
||||
nid = cpu_to_node(cpu);
|
||||
int nid = cpu_to_node(cpu);
|
||||
if (uv_hub_nmi_list[nid] == NULL) {
|
||||
uv_hub_nmi_list[nid] = kzalloc_node(size,
|
||||
GFP_KERNEL, nid);
|
||||
BUG_ON(!uv_hub_nmi_list[nid]);
|
||||
raw_spin_lock_init(&(uv_hub_nmi_list[nid]->nmi_lock));
|
||||
atomic_set(&uv_hub_nmi_list[nid]->cpu_owner, -1);
|
||||
uv_hub_nmi_list[nid]->hub_present = hubbed;
|
||||
uv_hub_nmi_list[nid]->pch_owner = (nid == 0);
|
||||
}
|
||||
uv_hub_nmi_per(cpu) = uv_hub_nmi_list[nid];
|
||||
}
|
||||
BUG_ON(!alloc_cpumask_var(&uv_nmi_cpu_mask, GFP_KERNEL));
|
||||
uv_register_nmi_notifier();
|
||||
}
|
||||
|
||||
/* Setup for UV Hub systems */
|
||||
void __init uv_nmi_setup(void)
|
||||
{
|
||||
uv_nmi_setup_mmrs();
|
||||
uv_nmi_setup_common(true);
|
||||
uv_register_nmi_notifier();
|
||||
pr_info("UV: Hub NMI enabled\n");
|
||||
}
|
||||
|
||||
/* Setup for UV Hubless systems */
|
||||
void __init uv_nmi_setup_hubless(void)
|
||||
{
|
||||
uv_nmi_setup_common(false);
|
||||
pch_base = xlate_dev_mem_ptr(PCH_PCR_GPIO_1_BASE);
|
||||
nmi_debug("UV: PCH base:%p from 0x%lx, GPP_D_0\n",
|
||||
pch_base, PCH_PCR_GPIO_1_BASE);
|
||||
if (uv_pch_init_enable)
|
||||
uv_init_hubless_pch_d0();
|
||||
uv_init_hubless_pch_io(GPI_NMI_ENA_GPP_D_0,
|
||||
STS_GPP_D_0_MASK, STS_GPP_D_0_MASK);
|
||||
uv_nmi_setup_hubless_intr();
|
||||
/* Ensure NMI enabled in Processor Interface Reg: */
|
||||
uv_reassert_nmi();
|
||||
uv_register_nmi_notifier();
|
||||
pr_info("UV: Hubless NMI enabled\n");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -816,13 +816,6 @@ config INTEL_SCU_IPC_UTIL
|
|||
low level access for debug work and updating the firmware. Say
|
||||
N unless you will be doing this on an Intel MID platform.
|
||||
|
||||
config GPIO_INTEL_PMIC
|
||||
bool "Intel PMIC GPIO support"
|
||||
depends on INTEL_SCU_IPC && GPIOLIB
|
||||
---help---
|
||||
Say Y here to support GPIO via the SCU IPC interface
|
||||
on Intel MID platforms.
|
||||
|
||||
config INTEL_MID_POWER_BUTTON
|
||||
tristate "power button driver for Intel MID platforms"
|
||||
depends on INTEL_SCU_IPC && INPUT
|
||||
|
|
|
|||
|
|
@ -50,7 +50,6 @@ obj-$(CONFIG_INTEL_SCU_IPC) += intel_scu_ipc.o
|
|||
obj-$(CONFIG_INTEL_SCU_IPC_UTIL) += intel_scu_ipcutil.o
|
||||
obj-$(CONFIG_INTEL_MFLD_THERMAL) += intel_mid_thermal.o
|
||||
obj-$(CONFIG_INTEL_IPS) += intel_ips.o
|
||||
obj-$(CONFIG_GPIO_INTEL_PMIC) += intel_pmic_gpio.o
|
||||
obj-$(CONFIG_XO1_RFKILL) += xo1-rfkill.o
|
||||
obj-$(CONFIG_XO15_EBOOK) += xo15-ebook.o
|
||||
obj-$(CONFIG_IBM_RTL) += ibm_rtl.o
|
||||
|
|
|
|||
|
|
@ -1,326 +0,0 @@
|
|||
/* Moorestown PMIC GPIO (access through IPC) driver
|
||||
* Copyright (c) 2008 - 2009, Intel Corporation.
|
||||
*
|
||||
* Author: Alek Du <alek.du@intel.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
/* Supports:
|
||||
* Moorestown platform PMIC chip
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/stddef.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/gpio/driver.h>
|
||||
#include <asm/intel_scu_ipc.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/intel_pmic_gpio.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
#define DRIVER_NAME "pmic_gpio"
|
||||
|
||||
/* register offset that IPC driver should use
|
||||
* 8 GPIO + 8 GPOSW (6 controllable) + 8GPO
|
||||
*/
|
||||
enum pmic_gpio_register {
|
||||
GPIO0 = 0xE0,
|
||||
GPIO7 = 0xE7,
|
||||
GPIOINT = 0xE8,
|
||||
GPOSWCTL0 = 0xEC,
|
||||
GPOSWCTL5 = 0xF1,
|
||||
GPO = 0xF4,
|
||||
};
|
||||
|
||||
/* bits definition for GPIO & GPOSW */
|
||||
#define GPIO_DRV 0x01
|
||||
#define GPIO_DIR 0x02
|
||||
#define GPIO_DIN 0x04
|
||||
#define GPIO_DOU 0x08
|
||||
#define GPIO_INTCTL 0x30
|
||||
#define GPIO_DBC 0xc0
|
||||
|
||||
#define GPOSW_DRV 0x01
|
||||
#define GPOSW_DOU 0x08
|
||||
#define GPOSW_RDRV 0x30
|
||||
|
||||
#define GPIO_UPDATE_TYPE 0x80000000
|
||||
|
||||
#define NUM_GPIO 24
|
||||
|
||||
struct pmic_gpio {
|
||||
struct mutex buslock;
|
||||
struct gpio_chip chip;
|
||||
void *gpiointr;
|
||||
int irq;
|
||||
unsigned irq_base;
|
||||
unsigned int update_type;
|
||||
u32 trigger_type;
|
||||
};
|
||||
|
||||
static void pmic_program_irqtype(int gpio, int type)
|
||||
{
|
||||
if (type & IRQ_TYPE_EDGE_RISING)
|
||||
intel_scu_ipc_update_register(GPIO0 + gpio, 0x20, 0x20);
|
||||
else
|
||||
intel_scu_ipc_update_register(GPIO0 + gpio, 0x00, 0x20);
|
||||
|
||||
if (type & IRQ_TYPE_EDGE_FALLING)
|
||||
intel_scu_ipc_update_register(GPIO0 + gpio, 0x10, 0x10);
|
||||
else
|
||||
intel_scu_ipc_update_register(GPIO0 + gpio, 0x00, 0x10);
|
||||
};
|
||||
|
||||
static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
if (offset >= 8) {
|
||||
pr_err("only pin 0-7 support input\n");
|
||||
return -1;/* we only have 8 GPIO can use as input */
|
||||
}
|
||||
return intel_scu_ipc_update_register(GPIO0 + offset,
|
||||
GPIO_DIR, GPIO_DIR);
|
||||
}
|
||||
|
||||
static int pmic_gpio_direction_output(struct gpio_chip *chip,
|
||||
unsigned offset, int value)
|
||||
{
|
||||
int rc = 0;
|
||||
|
||||
if (offset < 8)/* it is GPIO */
|
||||
rc = intel_scu_ipc_update_register(GPIO0 + offset,
|
||||
GPIO_DRV | (value ? GPIO_DOU : 0),
|
||||
GPIO_DRV | GPIO_DOU | GPIO_DIR);
|
||||
else if (offset < 16)/* it is GPOSW */
|
||||
rc = intel_scu_ipc_update_register(GPOSWCTL0 + offset - 8,
|
||||
GPOSW_DRV | (value ? GPOSW_DOU : 0),
|
||||
GPOSW_DRV | GPOSW_DOU | GPOSW_RDRV);
|
||||
else if (offset > 15 && offset < 24)/* it is GPO */
|
||||
rc = intel_scu_ipc_update_register(GPO,
|
||||
value ? 1 << (offset - 16) : 0,
|
||||
1 << (offset - 16));
|
||||
else {
|
||||
pr_err("invalid PMIC GPIO pin %d!\n", offset);
|
||||
WARN_ON(1);
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int pmic_gpio_get(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
u8 r;
|
||||
int ret;
|
||||
|
||||
/* we only have 8 GPIO pins we can use as input */
|
||||
if (offset >= 8)
|
||||
return -EOPNOTSUPP;
|
||||
ret = intel_scu_ipc_ioread8(GPIO0 + offset, &r);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
return r & GPIO_DIN;
|
||||
}
|
||||
|
||||
static void pmic_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
|
||||
{
|
||||
if (offset < 8)/* it is GPIO */
|
||||
intel_scu_ipc_update_register(GPIO0 + offset,
|
||||
GPIO_DRV | (value ? GPIO_DOU : 0),
|
||||
GPIO_DRV | GPIO_DOU);
|
||||
else if (offset < 16)/* it is GPOSW */
|
||||
intel_scu_ipc_update_register(GPOSWCTL0 + offset - 8,
|
||||
GPOSW_DRV | (value ? GPOSW_DOU : 0),
|
||||
GPOSW_DRV | GPOSW_DOU | GPOSW_RDRV);
|
||||
else if (offset > 15 && offset < 24) /* it is GPO */
|
||||
intel_scu_ipc_update_register(GPO,
|
||||
value ? 1 << (offset - 16) : 0,
|
||||
1 << (offset - 16));
|
||||
}
|
||||
|
||||
/*
|
||||
* This is called from genirq with pg->buslock locked and
|
||||
* irq_desc->lock held. We can not access the scu bus here, so we
|
||||
* store the change and update in the bus_sync_unlock() function below
|
||||
*/
|
||||
static int pmic_irq_type(struct irq_data *data, unsigned type)
|
||||
{
|
||||
struct pmic_gpio *pg = irq_data_get_irq_chip_data(data);
|
||||
u32 gpio = data->irq - pg->irq_base;
|
||||
|
||||
if (gpio >= pg->chip.ngpio)
|
||||
return -EINVAL;
|
||||
|
||||
pg->trigger_type = type;
|
||||
pg->update_type = gpio | GPIO_UPDATE_TYPE;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
|
||||
{
|
||||
struct pmic_gpio *pg = gpiochip_get_data(chip);
|
||||
|
||||
return pg->irq_base + offset;
|
||||
}
|
||||
|
||||
static void pmic_bus_lock(struct irq_data *data)
|
||||
{
|
||||
struct pmic_gpio *pg = irq_data_get_irq_chip_data(data);
|
||||
|
||||
mutex_lock(&pg->buslock);
|
||||
}
|
||||
|
||||
static void pmic_bus_sync_unlock(struct irq_data *data)
|
||||
{
|
||||
struct pmic_gpio *pg = irq_data_get_irq_chip_data(data);
|
||||
|
||||
if (pg->update_type) {
|
||||
unsigned int gpio = pg->update_type & ~GPIO_UPDATE_TYPE;
|
||||
|
||||
pmic_program_irqtype(gpio, pg->trigger_type);
|
||||
pg->update_type = 0;
|
||||
}
|
||||
mutex_unlock(&pg->buslock);
|
||||
}
|
||||
|
||||
/* the gpiointr register is read-clear, so just do nothing. */
|
||||
static void pmic_irq_unmask(struct irq_data *data) { }
|
||||
|
||||
static void pmic_irq_mask(struct irq_data *data) { }
|
||||
|
||||
static struct irq_chip pmic_irqchip = {
|
||||
.name = "PMIC-GPIO",
|
||||
.irq_mask = pmic_irq_mask,
|
||||
.irq_unmask = pmic_irq_unmask,
|
||||
.irq_set_type = pmic_irq_type,
|
||||
.irq_bus_lock = pmic_bus_lock,
|
||||
.irq_bus_sync_unlock = pmic_bus_sync_unlock,
|
||||
};
|
||||
|
||||
static irqreturn_t pmic_irq_handler(int irq, void *data)
|
||||
{
|
||||
struct pmic_gpio *pg = data;
|
||||
u8 intsts = *((u8 *)pg->gpiointr + 4);
|
||||
int gpio;
|
||||
irqreturn_t ret = IRQ_NONE;
|
||||
|
||||
for (gpio = 0; gpio < 8; gpio++) {
|
||||
if (intsts & (1 << gpio)) {
|
||||
pr_debug("pmic pin %d triggered\n", gpio);
|
||||
generic_handle_irq(pg->irq_base + gpio);
|
||||
ret = IRQ_HANDLED;
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int platform_pmic_gpio_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
int irq = platform_get_irq(pdev, 0);
|
||||
struct intel_pmic_gpio_platform_data *pdata = dev->platform_data;
|
||||
|
||||
struct pmic_gpio *pg;
|
||||
int retval;
|
||||
int i;
|
||||
|
||||
if (irq < 0) {
|
||||
dev_dbg(dev, "no IRQ line\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (!pdata || !pdata->gpio_base || !pdata->irq_base) {
|
||||
dev_dbg(dev, "incorrect or missing platform data\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pg = kzalloc(sizeof(*pg), GFP_KERNEL);
|
||||
if (!pg)
|
||||
return -ENOMEM;
|
||||
|
||||
dev_set_drvdata(dev, pg);
|
||||
|
||||
pg->irq = irq;
|
||||
/* setting up SRAM mapping for GPIOINT register */
|
||||
pg->gpiointr = ioremap_nocache(pdata->gpiointr, 8);
|
||||
if (!pg->gpiointr) {
|
||||
pr_err("Can not map GPIOINT\n");
|
||||
retval = -EINVAL;
|
||||
goto err2;
|
||||
}
|
||||
pg->irq_base = pdata->irq_base;
|
||||
pg->chip.label = "intel_pmic";
|
||||
pg->chip.direction_input = pmic_gpio_direction_input;
|
||||
pg->chip.direction_output = pmic_gpio_direction_output;
|
||||
pg->chip.get = pmic_gpio_get;
|
||||
pg->chip.set = pmic_gpio_set;
|
||||
pg->chip.to_irq = pmic_gpio_to_irq;
|
||||
pg->chip.base = pdata->gpio_base;
|
||||
pg->chip.ngpio = NUM_GPIO;
|
||||
pg->chip.can_sleep = 1;
|
||||
pg->chip.parent = dev;
|
||||
|
||||
mutex_init(&pg->buslock);
|
||||
|
||||
pg->chip.parent = dev;
|
||||
retval = gpiochip_add_data(&pg->chip, pg);
|
||||
if (retval) {
|
||||
pr_err("Can not add pmic gpio chip\n");
|
||||
goto err;
|
||||
}
|
||||
|
||||
retval = request_irq(pg->irq, pmic_irq_handler, 0, "pmic", pg);
|
||||
if (retval) {
|
||||
pr_warn("Interrupt request failed\n");
|
||||
goto fail_request_irq;
|
||||
}
|
||||
|
||||
for (i = 0; i < 8; i++) {
|
||||
irq_set_chip_and_handler_name(i + pg->irq_base,
|
||||
&pmic_irqchip,
|
||||
handle_simple_irq,
|
||||
"demux");
|
||||
irq_set_chip_data(i + pg->irq_base, pg);
|
||||
}
|
||||
return 0;
|
||||
|
||||
fail_request_irq:
|
||||
gpiochip_remove(&pg->chip);
|
||||
err:
|
||||
iounmap(pg->gpiointr);
|
||||
err2:
|
||||
kfree(pg);
|
||||
return retval;
|
||||
}
|
||||
|
||||
/* at the same time, register a platform driver
|
||||
* this supports the sfi 0.81 fw */
|
||||
static struct platform_driver platform_pmic_gpio_driver = {
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
},
|
||||
.probe = platform_pmic_gpio_probe,
|
||||
};
|
||||
|
||||
static int __init platform_pmic_gpio_init(void)
|
||||
{
|
||||
return platform_driver_register(&platform_pmic_gpio_driver);
|
||||
}
|
||||
subsys_initcall(platform_pmic_gpio_init);
|
||||
|
|
@ -1,15 +0,0 @@
|
|||
#ifndef LINUX_INTEL_PMIC_H
|
||||
#define LINUX_INTEL_PMIC_H
|
||||
|
||||
struct intel_pmic_gpio_platform_data {
|
||||
/* the first IRQ of the chip */
|
||||
unsigned irq_base;
|
||||
/* number assigned to the first GPIO */
|
||||
unsigned gpio_base;
|
||||
/* sram address for gpiointr register, the langwell chip will map
|
||||
* the PMIC spi GPIO expander's GPIOINTR register in sram.
|
||||
*/
|
||||
unsigned gpiointr;
|
||||
};
|
||||
|
||||
#endif
|
||||
Загрузка…
Ссылка в новой задаче