drm/msm/dpu: Avoid ABBA deadlock between IRQ modules
Handling of the interrupt callback lists is done in dpu_core_irq.c,
under the "cb_lock" spinlock. When these operations results in the need
for enableing or disabling the IRQ in the hardware the code jumps to
dpu_hw_interrupts.c, which protects its operations with "irq_lock"
spinlock.
When an interrupt fires, dpu_hw_intr_dispatch_irq() inspects the
hardware state while holding the "irq_lock" spinlock and jumps to
dpu_core_irq_callback_handler() to invoke the registered handlers, which
traverses the callback list under the "cb_lock" spinlock.
As such, in the event that these happens concurrently we'll end up with
a deadlock.
Prior to '1c1e7763a6d4 ("drm/msm/dpu: simplify IRQ enabling/disabling")'
the enable/disable of the hardware interrupt was done outside the
"cb_lock" region, optimitically by using an atomic enable-counter for
each interrupt and an warning print if someone changed the list between
the atomic_read and the time the operation concluded.
Rather than re-introducing the large array of atomics, this change
embraces the fact that dpu_core_irq and dpu_hw_interrupts are deeply
entangled and make them share the single "irq_lock".
Following this step it's suggested that we squash the two parts into a
single irq handling thing.
Fixes: 1c1e7763a6d4 ("drm/msm/dpu: simplify IRQ enabling/disabling")
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20210611170003.3539059-1-bjorn.andersson@linaro.org
Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Bjorn Andersson
Rob Clark
Родитель
e25e92e08e
Коммит
c96348a8fb
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@ -22,7 +22,6 @@ static void dpu_core_irq_callback_handler(void *arg, int irq_idx)
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struct dpu_kms *dpu_kms = arg;
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struct dpu_irq *irq_obj = &dpu_kms->irq_obj;
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struct dpu_irq_callback *cb;
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unsigned long irq_flags;
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VERB("irq_idx=%d\n", irq_idx);
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@ -34,11 +33,9 @@ static void dpu_core_irq_callback_handler(void *arg, int irq_idx)
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/*
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* Perform registered function callback
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*/
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spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags);
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list_for_each_entry(cb, &irq_obj->irq_cb_tbl[irq_idx], list)
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if (cb->func)
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cb->func(cb->arg, irq_idx);
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spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);
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}
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u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx, bool clear)
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@ -82,22 +79,21 @@ int dpu_core_irq_register_callback(struct dpu_kms *dpu_kms, int irq_idx,
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VERB("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx);
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spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags);
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irq_flags = dpu_kms->hw_intr->ops.lock(dpu_kms->hw_intr);
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trace_dpu_core_irq_register_callback(irq_idx, register_irq_cb);
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list_del_init(®ister_irq_cb->list);
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list_add_tail(®ister_irq_cb->list,
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&dpu_kms->irq_obj.irq_cb_tbl[irq_idx]);
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if (list_is_first(®ister_irq_cb->list,
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&dpu_kms->irq_obj.irq_cb_tbl[irq_idx])) {
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int ret = dpu_kms->hw_intr->ops.enable_irq(
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int ret = dpu_kms->hw_intr->ops.enable_irq_locked(
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dpu_kms->hw_intr,
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irq_idx);
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if (ret)
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DPU_ERROR("Fail to enable IRQ for irq_idx:%d\n",
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irq_idx);
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}
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spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);
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dpu_kms->hw_intr->ops.unlock(dpu_kms->hw_intr, irq_flags);
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return 0;
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}
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@ -127,12 +123,12 @@ int dpu_core_irq_unregister_callback(struct dpu_kms *dpu_kms, int irq_idx,
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VERB("[%pS] irq_idx=%d\n", __builtin_return_address(0), irq_idx);
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spin_lock_irqsave(&dpu_kms->irq_obj.cb_lock, irq_flags);
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irq_flags = dpu_kms->hw_intr->ops.lock(dpu_kms->hw_intr);
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trace_dpu_core_irq_unregister_callback(irq_idx, register_irq_cb);
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list_del_init(®ister_irq_cb->list);
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/* empty callback list but interrupt is still enabled */
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if (list_empty(&dpu_kms->irq_obj.irq_cb_tbl[irq_idx])) {
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int ret = dpu_kms->hw_intr->ops.disable_irq(
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int ret = dpu_kms->hw_intr->ops.disable_irq_locked(
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dpu_kms->hw_intr,
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irq_idx);
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if (ret)
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@ -140,7 +136,7 @@ int dpu_core_irq_unregister_callback(struct dpu_kms *dpu_kms, int irq_idx,
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irq_idx);
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VERB("irq_idx=%d ret=%d\n", irq_idx, ret);
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}
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spin_unlock_irqrestore(&dpu_kms->irq_obj.cb_lock, irq_flags);
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dpu_kms->hw_intr->ops.unlock(dpu_kms->hw_intr, irq_flags);
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return 0;
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}
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@ -164,7 +160,8 @@ static void dpu_disable_all_irqs(struct dpu_kms *dpu_kms)
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#ifdef CONFIG_DEBUG_FS
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static int dpu_debugfs_core_irq_show(struct seq_file *s, void *v)
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{
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struct dpu_irq *irq_obj = s->private;
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struct dpu_kms *dpu_kms = s->private;
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struct dpu_irq *irq_obj = &dpu_kms->irq_obj;
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struct dpu_irq_callback *cb;
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unsigned long irq_flags;
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int i, irq_count, cb_count;
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@ -173,12 +170,12 @@ static int dpu_debugfs_core_irq_show(struct seq_file *s, void *v)
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return 0;
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for (i = 0; i < irq_obj->total_irqs; i++) {
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spin_lock_irqsave(&irq_obj->cb_lock, irq_flags);
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irq_flags = dpu_kms->hw_intr->ops.lock(dpu_kms->hw_intr);
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cb_count = 0;
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irq_count = atomic_read(&irq_obj->irq_counts[i]);
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list_for_each_entry(cb, &irq_obj->irq_cb_tbl[i], list)
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cb_count++;
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spin_unlock_irqrestore(&irq_obj->cb_lock, irq_flags);
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dpu_kms->hw_intr->ops.unlock(dpu_kms->hw_intr, irq_flags);
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if (irq_count || cb_count)
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seq_printf(s, "idx:%d irq:%d cb:%d\n",
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@ -193,7 +190,7 @@ DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_core_irq);
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void dpu_debugfs_core_irq_init(struct dpu_kms *dpu_kms,
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struct dentry *parent)
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{
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debugfs_create_file("core_irq", 0600, parent, &dpu_kms->irq_obj,
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debugfs_create_file("core_irq", 0600, parent, dpu_kms,
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&dpu_debugfs_core_irq_fops);
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}
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#endif
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@ -207,8 +204,6 @@ void dpu_core_irq_preinstall(struct dpu_kms *dpu_kms)
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dpu_disable_all_irqs(dpu_kms);
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pm_runtime_put_sync(&dpu_kms->pdev->dev);
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spin_lock_init(&dpu_kms->irq_obj.cb_lock);
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/* Create irq callbacks for all possible irq_idx */
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dpu_kms->irq_obj.total_irqs = dpu_kms->hw_intr->total_irqs;
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dpu_kms->irq_obj.irq_cb_tbl = kcalloc(dpu_kms->irq_obj.total_irqs,
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@ -205,10 +205,9 @@ static void dpu_hw_intr_dispatch_irq(struct dpu_hw_intr *intr,
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spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
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}
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static int dpu_hw_intr_enable_irq(struct dpu_hw_intr *intr, int irq_idx)
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static int dpu_hw_intr_enable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
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{
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int reg_idx;
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unsigned long irq_flags;
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const struct dpu_intr_reg *reg;
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const char *dbgstr = NULL;
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uint32_t cache_irq_mask;
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@ -221,10 +220,16 @@ static int dpu_hw_intr_enable_irq(struct dpu_hw_intr *intr, int irq_idx)
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return -EINVAL;
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}
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/*
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* The cache_irq_mask and hardware RMW operations needs to be done
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* under irq_lock and it's the caller's responsibility to ensure that's
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* held.
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*/
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assert_spin_locked(&intr->irq_lock);
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reg_idx = DPU_IRQ_REG(irq_idx);
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reg = &dpu_intr_set[reg_idx];
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spin_lock_irqsave(&intr->irq_lock, irq_flags);
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cache_irq_mask = intr->cache_irq_mask[reg_idx];
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if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) {
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dbgstr = "DPU IRQ already set:";
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@ -242,7 +247,6 @@ static int dpu_hw_intr_enable_irq(struct dpu_hw_intr *intr, int irq_idx)
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intr->cache_irq_mask[reg_idx] = cache_irq_mask;
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}
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spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
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pr_debug("%s MASK:0x%.8lx, CACHE-MASK:0x%.8x\n", dbgstr,
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DPU_IRQ_MASK(irq_idx), cache_irq_mask);
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@ -250,7 +254,7 @@ static int dpu_hw_intr_enable_irq(struct dpu_hw_intr *intr, int irq_idx)
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return 0;
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}
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static int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx)
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static int dpu_hw_intr_disable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
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{
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int reg_idx;
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const struct dpu_intr_reg *reg;
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@ -265,6 +269,13 @@ static int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx)
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return -EINVAL;
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}
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/*
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* The cache_irq_mask and hardware RMW operations needs to be done
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* under irq_lock and it's the caller's responsibility to ensure that's
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* held.
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*/
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assert_spin_locked(&intr->irq_lock);
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reg_idx = DPU_IRQ_REG(irq_idx);
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reg = &dpu_intr_set[reg_idx];
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@ -292,25 +303,6 @@ static int dpu_hw_intr_disable_irq_nolock(struct dpu_hw_intr *intr, int irq_idx)
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return 0;
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}
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static int dpu_hw_intr_disable_irq(struct dpu_hw_intr *intr, int irq_idx)
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{
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unsigned long irq_flags;
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if (!intr)
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return -EINVAL;
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if (irq_idx < 0 || irq_idx >= intr->total_irqs) {
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pr_err("invalid IRQ index: [%d]\n", irq_idx);
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return -EINVAL;
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}
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spin_lock_irqsave(&intr->irq_lock, irq_flags);
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dpu_hw_intr_disable_irq_nolock(intr, irq_idx);
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spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
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return 0;
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}
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static int dpu_hw_intr_clear_irqs(struct dpu_hw_intr *intr)
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{
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int i;
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@ -382,14 +374,30 @@ static u32 dpu_hw_intr_get_interrupt_status(struct dpu_hw_intr *intr,
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return intr_status;
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}
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static unsigned long dpu_hw_intr_lock(struct dpu_hw_intr *intr)
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{
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unsigned long irq_flags;
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spin_lock_irqsave(&intr->irq_lock, irq_flags);
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return irq_flags;
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}
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static void dpu_hw_intr_unlock(struct dpu_hw_intr *intr, unsigned long irq_flags)
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{
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spin_unlock_irqrestore(&intr->irq_lock, irq_flags);
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}
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static void __setup_intr_ops(struct dpu_hw_intr_ops *ops)
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{
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ops->enable_irq = dpu_hw_intr_enable_irq;
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ops->disable_irq = dpu_hw_intr_disable_irq;
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ops->enable_irq_locked = dpu_hw_intr_enable_irq_locked;
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ops->disable_irq_locked = dpu_hw_intr_disable_irq_locked;
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ops->dispatch_irqs = dpu_hw_intr_dispatch_irq;
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ops->clear_all_irqs = dpu_hw_intr_clear_irqs;
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ops->disable_all_irqs = dpu_hw_intr_disable_irqs;
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ops->get_interrupt_status = dpu_hw_intr_get_interrupt_status;
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ops->lock = dpu_hw_intr_lock;
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ops->unlock = dpu_hw_intr_unlock;
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}
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static void __intr_offset(struct dpu_mdss_cfg *m,
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@ -45,7 +45,7 @@ struct dpu_hw_intr_ops {
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* @irq_idx: Lookup irq index return from irq_idx_lookup
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* @return: 0 for success, otherwise failure
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*/
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int (*enable_irq)(
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int (*enable_irq_locked)(
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struct dpu_hw_intr *intr,
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int irq_idx);
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@ -55,7 +55,7 @@ struct dpu_hw_intr_ops {
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* @irq_idx: Lookup irq index return from irq_idx_lookup
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* @return: 0 for success, otherwise failure
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*/
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int (*disable_irq)(
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int (*disable_irq_locked)(
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struct dpu_hw_intr *intr,
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int irq_idx);
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@ -100,6 +100,22 @@ struct dpu_hw_intr_ops {
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struct dpu_hw_intr *intr,
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int irq_idx,
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bool clear);
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/**
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* lock - take the IRQ lock
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* @intr: HW interrupt handle
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* @return: irq_flags for the taken spinlock
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*/
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unsigned long (*lock)(
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struct dpu_hw_intr *intr);
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/**
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* unlock - take the IRQ lock
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* @intr: HW interrupt handle
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* @irq_flags: the irq_flags returned from lock
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*/
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void (*unlock)(
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struct dpu_hw_intr *intr, unsigned long irq_flags);
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};
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/**
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@ -82,14 +82,12 @@ struct dpu_irq_callback {
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* struct dpu_irq: IRQ structure contains callback registration info
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* @total_irq: total number of irq_idx obtained from HW interrupts mapping
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* @irq_cb_tbl: array of IRQ callbacks setting
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* @cb_lock: callback lock
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* @debugfs_file: debugfs file for irq statistics
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*/
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struct dpu_irq {
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u32 total_irqs;
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struct list_head *irq_cb_tbl;
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atomic_t *irq_counts;
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spinlock_t cb_lock;
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};
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struct dpu_kms {
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