x86/cpu: Create Hygon Dhyana architecture support file
Add x86 architecture support for a new processor: Hygon Dhyana Family 18h. Carve out initialization code needed by Dhyana into a separate compilation unit. To identify Hygon Dhyana CPU, add a new vendor type X86_VENDOR_HYGON. Since Dhyana uses AMD functionality to a large degree, select CPU_SUP_AMD which provides that functionality. [ bp: drop explicit license statement as it has an SPDX tag already. ] Signed-off-by: Pu Wen <puwen@hygon.cn> Reviewed-by: Borislav Petkov <bp@suse.de> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: tglx@linutronix.de Cc: mingo@redhat.com Cc: hpa@zytor.com Cc: x86@kernel.org Cc: thomas.lendacky@amd.com Link: https://lkml.kernel.org/r/1a882065223bacbde5726f3beaa70cebd8dcd814.1537533369.git.puwen@hygon.cn
This commit is contained in:
Pu Wen
Borislav Petkov
Родитель
7876320f88
Коммит
c9661c1e80
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@ -6762,6 +6762,12 @@ S: Maintained
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F: mm/memory-failure.c
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F: mm/hwpoison-inject.c
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HYGON PROCESSOR SUPPORT
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M: Pu Wen <puwen@hygon.cn>
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L: linux-kernel@vger.kernel.org
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S: Maintained
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F: arch/x86/kernel/cpu/hygon.c
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Hyper-V CORE AND DRIVERS
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M: "K. Y. Srinivasan" <kys@microsoft.com>
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M: Haiyang Zhang <haiyangz@microsoft.com>
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@ -426,6 +426,20 @@ config CPU_SUP_AMD
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If unsure, say N.
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config CPU_SUP_HYGON
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default y
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bool "Support Hygon processors" if PROCESSOR_SELECT
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select CPU_SUP_AMD
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help
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This enables detection, tunings and quirks for Hygon processors
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You need this enabled if you want your kernel to run on an
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Hygon CPU. Disabling this option on other types of CPUs
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makes the kernel a tiny bit smaller. Disabling it on an Hygon
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CPU might render the kernel unbootable.
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If unsure, say N.
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config CPU_SUP_CENTAUR
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default y
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bool "Support Centaur processors" if PROCESSOR_SELECT
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@ -155,7 +155,8 @@ enum cpuid_regs_idx {
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#define X86_VENDOR_CENTAUR 5
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#define X86_VENDOR_TRANSMETA 7
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#define X86_VENDOR_NSC 8
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#define X86_VENDOR_NUM 9
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#define X86_VENDOR_HYGON 9
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#define X86_VENDOR_NUM 10
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#define X86_VENDOR_UNKNOWN 0xff
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@ -30,6 +30,7 @@ obj-$(CONFIG_X86_FEATURE_NAMES) += capflags.o powerflags.o
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obj-$(CONFIG_CPU_SUP_INTEL) += intel.o intel_pconfig.o
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obj-$(CONFIG_CPU_SUP_AMD) += amd.o
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obj-$(CONFIG_CPU_SUP_HYGON) += hygon.o
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obj-$(CONFIG_CPU_SUP_CYRIX_32) += cyrix.o
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obj-$(CONFIG_CPU_SUP_CENTAUR) += centaur.o
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obj-$(CONFIG_CPU_SUP_TRANSMETA_32) += transmeta.o
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@ -0,0 +1,405 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Hygon Processor Support for Linux
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*
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* Copyright (C) 2018 Chengdu Haiguang IC Design Co., Ltd.
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*
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* Author: Pu Wen <puwen@hygon.cn>
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*/
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#include <linux/io.h>
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#include <asm/cpu.h>
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#include <asm/smp.h>
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#include <asm/cacheinfo.h>
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#include <asm/spec-ctrl.h>
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#include <asm/delay.h>
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#ifdef CONFIG_X86_64
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# include <asm/set_memory.h>
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#endif
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#include "cpu.h"
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/*
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* nodes_per_socket: Stores the number of nodes per socket.
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* Refer to CPUID Fn8000_001E_ECX Node Identifiers[10:8]
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*/
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static u32 nodes_per_socket = 1;
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#ifdef CONFIG_NUMA
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/*
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* To workaround broken NUMA config. Read the comment in
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* srat_detect_node().
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*/
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static int nearby_node(int apicid)
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{
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int i, node;
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for (i = apicid - 1; i >= 0; i--) {
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node = __apicid_to_node[i];
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if (node != NUMA_NO_NODE && node_online(node))
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return node;
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}
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for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
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node = __apicid_to_node[i];
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if (node != NUMA_NO_NODE && node_online(node))
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return node;
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}
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return first_node(node_online_map); /* Shouldn't happen */
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}
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#endif
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static void hygon_get_topology_early(struct cpuinfo_x86 *c)
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{
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if (cpu_has(c, X86_FEATURE_TOPOEXT))
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smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1;
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}
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/*
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* Fixup core topology information for
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* (1) Hygon multi-node processors
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* Assumption: Number of cores in each internal node is the same.
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* (2) Hygon processors supporting compute units
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*/
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static void hygon_get_topology(struct cpuinfo_x86 *c)
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{
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u8 node_id;
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int cpu = smp_processor_id();
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/* get information required for multi-node processors */
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if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
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int err;
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u32 eax, ebx, ecx, edx;
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cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
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node_id = ecx & 0xff;
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c->cpu_core_id = ebx & 0xff;
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if (smp_num_siblings > 1)
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c->x86_max_cores /= smp_num_siblings;
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/*
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* In case leaf B is available, use it to derive
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* topology information.
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*/
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err = detect_extended_topology(c);
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if (!err)
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c->x86_coreid_bits = get_count_order(c->x86_max_cores);
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} else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
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u64 value;
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rdmsrl(MSR_FAM10H_NODE_ID, value);
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node_id = value & 7;
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per_cpu(cpu_llc_id, cpu) = node_id;
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} else
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return;
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if (nodes_per_socket > 1)
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set_cpu_cap(c, X86_FEATURE_AMD_DCM);
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}
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/*
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* On Hygon setup the lower bits of the APIC id distinguish the cores.
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* Assumes number of cores is a power of two.
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*/
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static void hygon_detect_cmp(struct cpuinfo_x86 *c)
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{
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unsigned int bits;
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int cpu = smp_processor_id();
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bits = c->x86_coreid_bits;
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/* Low order bits define the core id (index of core in socket) */
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c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
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/* Convert the initial APIC ID into the socket ID */
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c->phys_proc_id = c->initial_apicid >> bits;
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/* use socket ID also for last level cache */
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per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
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}
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static void srat_detect_node(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_NUMA
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int cpu = smp_processor_id();
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int node;
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unsigned int apicid = c->apicid;
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node = numa_cpu_node(cpu);
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if (node == NUMA_NO_NODE)
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node = per_cpu(cpu_llc_id, cpu);
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/*
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* On multi-fabric platform (e.g. Numascale NumaChip) a
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* platform-specific handler needs to be called to fixup some
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* IDs of the CPU.
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*/
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if (x86_cpuinit.fixup_cpu_id)
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x86_cpuinit.fixup_cpu_id(c, node);
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if (!node_online(node)) {
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/*
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* Two possibilities here:
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*
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* - The CPU is missing memory and no node was created. In
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* that case try picking one from a nearby CPU.
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*
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* - The APIC IDs differ from the HyperTransport node IDs.
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* Assume they are all increased by a constant offset, but
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* in the same order as the HT nodeids. If that doesn't
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* result in a usable node fall back to the path for the
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* previous case.
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*
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* This workaround operates directly on the mapping between
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* APIC ID and NUMA node, assuming certain relationship
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* between APIC ID, HT node ID and NUMA topology. As going
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* through CPU mapping may alter the outcome, directly
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* access __apicid_to_node[].
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*/
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int ht_nodeid = c->initial_apicid;
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if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
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node = __apicid_to_node[ht_nodeid];
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/* Pick a nearby node */
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if (!node_online(node))
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node = nearby_node(apicid);
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}
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numa_set_node(cpu, node);
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#endif
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}
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static void early_init_hygon_mc(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_SMP
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unsigned int bits, ecx;
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/* Multi core CPU? */
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if (c->extended_cpuid_level < 0x80000008)
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return;
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ecx = cpuid_ecx(0x80000008);
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c->x86_max_cores = (ecx & 0xff) + 1;
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/* CPU telling us the core id bits shift? */
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bits = (ecx >> 12) & 0xF;
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/* Otherwise recompute */
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if (bits == 0) {
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while ((1 << bits) < c->x86_max_cores)
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bits++;
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}
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c->x86_coreid_bits = bits;
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#endif
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}
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static void bsp_init_hygon(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_X86_64
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unsigned long long tseg;
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/*
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* Split up direct mapping around the TSEG SMM area.
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* Don't do it for gbpages because there seems very little
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* benefit in doing so.
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*/
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if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
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unsigned long pfn = tseg >> PAGE_SHIFT;
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pr_debug("tseg: %010llx\n", tseg);
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if (pfn_range_is_mapped(pfn, pfn + 1))
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set_memory_4k((unsigned long)__va(tseg), 1);
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}
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#endif
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if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
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u64 val;
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rdmsrl(MSR_K7_HWCR, val);
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if (!(val & BIT(24)))
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pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
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}
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if (cpu_has(c, X86_FEATURE_MWAITX))
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use_mwaitx_delay();
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if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
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u32 ecx;
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ecx = cpuid_ecx(0x8000001e);
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nodes_per_socket = ((ecx >> 8) & 7) + 1;
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} else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
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u64 value;
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rdmsrl(MSR_FAM10H_NODE_ID, value);
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nodes_per_socket = ((value >> 3) & 7) + 1;
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}
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if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) &&
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!boot_cpu_has(X86_FEATURE_VIRT_SSBD)) {
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/*
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* Try to cache the base value so further operations can
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* avoid RMW. If that faults, do not enable SSBD.
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*/
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if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
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setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD);
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setup_force_cpu_cap(X86_FEATURE_SSBD);
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x86_amd_ls_cfg_ssbd_mask = 1ULL << 10;
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}
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}
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}
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static void early_init_hygon(struct cpuinfo_x86 *c)
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{
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u32 dummy;
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early_init_hygon_mc(c);
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set_cpu_cap(c, X86_FEATURE_K8);
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rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
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/*
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* c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
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* with P/T states and does not stop in deep C-states
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*/
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if (c->x86_power & (1 << 8)) {
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set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
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}
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/* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
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if (c->x86_power & BIT(12))
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set_cpu_cap(c, X86_FEATURE_ACC_POWER);
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#ifdef CONFIG_X86_64
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set_cpu_cap(c, X86_FEATURE_SYSCALL32);
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#endif
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#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
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/*
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* ApicID can always be treated as an 8-bit value for Hygon APIC So, we
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* can safely set X86_FEATURE_EXTD_APICID unconditionally.
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*/
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if (boot_cpu_has(X86_FEATURE_APIC))
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set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
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#endif
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/*
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* This is only needed to tell the kernel whether to use VMCALL
|
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* and VMMCALL. VMMCALL is never executed except under virt, so
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* we can set it unconditionally.
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*/
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set_cpu_cap(c, X86_FEATURE_VMMCALL);
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hygon_get_topology_early(c);
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}
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static void init_hygon(struct cpuinfo_x86 *c)
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{
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early_init_hygon(c);
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/*
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* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
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* 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
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*/
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clear_cpu_cap(c, 0*32+31);
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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/* get apicid instead of initial apic id from cpuid */
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c->apicid = hard_smp_processor_id();
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set_cpu_cap(c, X86_FEATURE_ZEN);
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set_cpu_cap(c, X86_FEATURE_CPB);
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cpu_detect_cache_sizes(c);
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hygon_detect_cmp(c);
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hygon_get_topology(c);
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srat_detect_node(c);
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if (cpu_has(c, X86_FEATURE_XMM2)) {
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unsigned long long val;
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int ret;
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|
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/*
|
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* A serializing LFENCE has less overhead than MFENCE, so
|
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* use it for execution serialization. On families which
|
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* don't have that MSR, LFENCE is already serializing.
|
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* msr_set_bit() uses the safe accessors, too, even if the MSR
|
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* is not present.
|
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*/
|
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msr_set_bit(MSR_F10H_DECFG,
|
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MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
|
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|
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/*
|
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* Verify that the MSR write was successful (could be running
|
||||
* under a hypervisor) and only then assume that LFENCE is
|
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* serializing.
|
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*/
|
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ret = rdmsrl_safe(MSR_F10H_DECFG, &val);
|
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if (!ret && (val & MSR_F10H_DECFG_LFENCE_SERIALIZE)) {
|
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/* A serializing LFENCE stops RDTSC speculation */
|
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set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
|
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} else {
|
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/* MFENCE stops RDTSC speculation */
|
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set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
|
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}
|
||||
}
|
||||
|
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/*
|
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* Hygon processors have APIC timer running in deep C states.
|
||||
*/
|
||||
set_cpu_cap(c, X86_FEATURE_ARAT);
|
||||
|
||||
/* Hygon CPUs don't reset SS attributes on SYSRET, Xen does. */
|
||||
if (!cpu_has(c, X86_FEATURE_XENPV))
|
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set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
|
||||
}
|
||||
|
||||
static void cpu_detect_tlb_hygon(struct cpuinfo_x86 *c)
|
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{
|
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u32 ebx, eax, ecx, edx;
|
||||
u16 mask = 0xfff;
|
||||
|
||||
if (c->extended_cpuid_level < 0x80000006)
|
||||
return;
|
||||
|
||||
cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
|
||||
|
||||
tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
|
||||
tlb_lli_4k[ENTRIES] = ebx & mask;
|
||||
|
||||
/* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
|
||||
if (!((eax >> 16) & mask))
|
||||
tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
|
||||
else
|
||||
tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
|
||||
|
||||
/* a 4M entry uses two 2M entries */
|
||||
tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
|
||||
|
||||
/* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
|
||||
if (!(eax & mask)) {
|
||||
cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
|
||||
tlb_lli_2m[ENTRIES] = eax & 0xff;
|
||||
} else
|
||||
tlb_lli_2m[ENTRIES] = eax & mask;
|
||||
|
||||
tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
|
||||
}
|
||||
|
||||
static const struct cpu_dev hygon_cpu_dev = {
|
||||
.c_vendor = "Hygon",
|
||||
.c_ident = { "HygonGenuine" },
|
||||
.c_early_init = early_init_hygon,
|
||||
.c_detect_tlb = cpu_detect_tlb_hygon,
|
||||
.c_bsp_init = bsp_init_hygon,
|
||||
.c_init = init_hygon,
|
||||
.c_x86_vendor = X86_VENDOR_HYGON,
|
||||
};
|
||||
|
||||
cpu_dev_register(hygon_cpu_dev);
|
||||
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Ссылка в новой задаче