dmaengine: IOATDMA: revise channel reset workaround on CB3.3 platforms
Previously we unloaded the interrupts and reloaded in order to work around a channel reset bug that cleared the MSIX table. This approach just isn't practical when a reset needs to happen in the error handler that just happens to be running in interrupt context (bottom half). It looks like we can work around the hardware issue by just storing a shadow copy of the MSIX table and restore it after reset. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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dd4645ebb7
Коммит
c997e30e7f
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@ -804,40 +804,6 @@ ioat_tx_status(struct dma_chan *c, dma_cookie_t cookie,
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return dma_cookie_status(c, cookie, txstate);
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}
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static int ioat_irq_reinit(struct ioatdma_device *ioat_dma)
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{
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struct pci_dev *pdev = ioat_dma->pdev;
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int irq = pdev->irq, i;
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if (!is_bwd_ioat(pdev))
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return 0;
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switch (ioat_dma->irq_mode) {
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case IOAT_MSIX:
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for (i = 0; i < ioat_dma->dma_dev.chancnt; i++) {
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struct msix_entry *msix = &ioat_dma->msix_entries[i];
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struct ioatdma_chan *ioat_chan;
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ioat_chan = ioat_chan_by_index(ioat_dma, i);
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devm_free_irq(&pdev->dev, msix->vector, ioat_chan);
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}
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pci_disable_msix(pdev);
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break;
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case IOAT_MSI:
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pci_disable_msi(pdev);
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/* fall through */
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case IOAT_INTX:
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devm_free_irq(&pdev->dev, irq, ioat_dma);
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break;
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default:
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return 0;
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}
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ioat_dma->irq_mode = IOAT_NOIRQ;
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return ioat_dma_setup_interrupts(ioat_dma);
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}
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int ioat_reset_hw(struct ioatdma_chan *ioat_chan)
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{
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/* throw away whatever the channel was doing and get it
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@ -877,9 +843,21 @@ int ioat_reset_hw(struct ioatdma_chan *ioat_chan)
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}
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}
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if (is_bwd_ioat(pdev) && (ioat_dma->irq_mode == IOAT_MSIX)) {
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ioat_dma->msixtba0 = readq(ioat_dma->reg_base + 0x1000);
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ioat_dma->msixdata0 = readq(ioat_dma->reg_base + 0x1008);
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ioat_dma->msixpba = readq(ioat_dma->reg_base + 0x1800);
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}
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err = ioat_reset_sync(ioat_chan, msecs_to_jiffies(200));
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if (!err)
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err = ioat_irq_reinit(ioat_dma);
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if (!err) {
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if (is_bwd_ioat(pdev) && (ioat_dma->irq_mode == IOAT_MSIX)) {
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writeq(ioat_dma->msixtba0, ioat_dma->reg_base + 0x1000);
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writeq(ioat_dma->msixdata0, ioat_dma->reg_base + 0x1008);
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writeq(ioat_dma->msixpba, ioat_dma->reg_base + 0x1800);
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}
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}
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if (err)
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dev_err(&pdev->dev, "Failed to reset: %d\n", err);
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@ -86,6 +86,11 @@ struct ioatdma_device {
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struct dca_provider *dca;
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enum ioat_irq_mode irq_mode;
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u32 cap;
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/* shadow version for CB3.3 chan reset errata workaround */
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u64 msixtba0;
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u64 msixdata0;
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u32 msixpba;
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};
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struct ioat_descs {
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