[SCSI] qla2xxx: Fix for memory wedge on fw halt for ISP82XX
Signed-off-by: Swapnil Nagle <swapnil.nagle@qlogic.com> Signed-off-by: Karen Higgins <karen.higgins@qlogic.com> Signed-off-by: Madhuranath Iyengar <Madhu.Iyengar@qlogic.com> Signed-off-by: James Bottomley <James.Bottomley@suse.de>
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@ -1079,11 +1079,55 @@ qla82xx_pinit_from_rom(scsi_qla_host_t *vha)
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/* Halt all the indiviual PEGs and other blocks of the ISP */
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/* Halt all the indiviual PEGs and other blocks of the ISP */
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qla82xx_rom_lock(ha);
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qla82xx_rom_lock(ha);
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/* mask all niu interrupts */
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qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
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/* disable xge rx/tx */
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qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
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/* disable xg1 rx/tx */
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qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
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/* halt sre */
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val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
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qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
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/* halt epg */
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qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
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/* halt timers */
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qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
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qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
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qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
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qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
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qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
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/* halt pegs */
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qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
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qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
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qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
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qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
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qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
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/* big hammer */
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msleep(1000);
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if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
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if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
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/* don't reset CAM block on reset */
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/* don't reset CAM block on reset */
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qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
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qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
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else
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else
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qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
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qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
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/* reset ms */
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val = qla82xx_rd_32(ha, QLA82XX_CRB_QDR_NET + 0xe4);
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val |= (1 << 1);
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qla82xx_wr_32(ha, QLA82XX_CRB_QDR_NET + 0xe4, val);
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msleep(20);
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/* unreset ms */
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val = qla82xx_rd_32(ha, QLA82XX_CRB_QDR_NET + 0xe4);
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val &= ~(1 << 1);
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qla82xx_wr_32(ha, QLA82XX_CRB_QDR_NET + 0xe4, val);
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msleep(20);
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qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
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qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
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/* Read the signature value from the flash.
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/* Read the signature value from the flash.
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